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Merge branch 'master' into verilog_testbench

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tangxifan 2021-07-01 21:11:12 -06:00 committed by GitHub
parent 1d281765ea 947f078a7e
commit b7356d23aa
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openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
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@ -230,7 +230,7 @@ void print_verilog_random_testbench_reset_stimuli(std::fstream& fp,
*/
fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl;
fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl;
print_verilog_wire_connection(fp, reset_port, reset_port, true);
print_verilog_register_connection(fp, reset_port, reset_port, true);
fp << "\tend" << std::endl;
}