tangxifan
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546350ae41
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[FPGA-Verilog] Revert back to the previous precomputing strategy for shift register clocks
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2021-10-10 23:19:39 -07:00 |
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tangxifan
|
40fd89fdb4
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[arch] Update fabric key for multi-region
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2021-10-10 22:03:49 -07:00 |
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tangxifan
|
b9c540ec3f
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[Engine] Upgrade fabric key writer to support BL/WL shift register banks
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2021-10-10 21:14:14 -07:00 |
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tangxifan
|
202b50c0e3
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[FPGA-Verilog] Fixed a weird bug which causes totally different results in fixed and auto shift register clock freq; However, this is a dirty fix. Require further study to know why
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2021-10-10 20:57:23 -07:00 |
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tangxifan
|
4e2df9d69c
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[Lib] Bug fix in unintialized memory in fabric key
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2021-10-10 17:59:11 -07:00 |
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tangxifan
|
57159fc121
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[Doc] Update documentation for the new syntax in configuration protocol and fabric key file format
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2021-10-10 17:46:45 -07:00 |
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tangxifan
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de3275e9ba
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[FPGA-Verilog] Fixed a critical in verilog testbench which caused the last bit of bitstream skipped when loading to shift register chains
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2021-10-10 16:56:07 -07:00 |
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tangxifan
|
1c46a92559
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[FPGA-Bitstream] Bug fix
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2021-10-09 21:59:56 -07:00 |
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tangxifan
|
6aa4991314
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[FPGA-Verilog] Bug fix
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2021-10-09 21:34:07 -07:00 |
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tangxifan
|
7810f376c8
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[FPGA-Bitstream] Patch code comments
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2021-10-09 21:03:01 -07:00 |
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tangxifan
|
8f9e564cd5
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[Test] Add the new test to basic regression test
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2021-10-09 20:45:23 -07:00 |
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tangxifan
|
6122863548
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[Test] Add a test case to validate the multi-shift-register-chain QL memory bank
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2021-10-09 20:44:28 -07:00 |
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tangxifan
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82e77b42c5
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[Arch] Add an example architecture which uses multiple shift register chain for a single-ql-bank FPGA
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2021-10-09 20:43:55 -07:00 |
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tangxifan
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34575f7222
|
[FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank
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2021-10-09 20:39:45 -07:00 |
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tangxifan
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aac74d9163
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[Engine] Bug fix
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2021-10-09 18:46:20 -07:00 |
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tangxifan
|
fa08f44107
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[Engine] Bug fix
|
2021-10-09 16:58:56 -07:00 |
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tangxifan
|
19a551e641
|
[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region
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2021-10-09 16:44:04 -07:00 |
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tangxifan
|
932beb480a
|
[Engine] Add fast look-up to the shift register bank data structure
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2021-10-08 22:00:01 -07:00 |
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tangxifan
|
e3ff40d9e0
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[Engine] Add missing return value
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2021-10-08 20:17:55 -07:00 |
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tangxifan
|
39a69e0d88
|
[Engine] Upgrading fabric generator to support customizable shift register banks from fabric key and configuration protocols
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2021-10-08 17:58:06 -07:00 |
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tangxifan
|
8f5f30792f
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[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
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2021-10-08 15:25:37 -07:00 |
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tangxifan
|
f7484d4323
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[Engine] Update the key memory data structure to contain shift register bank general information
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2021-10-08 10:42:18 -07:00 |
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tangxifan
|
92eebd9abb
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[Lib] Upgrade fabric key writer to support the BL/WL shift register banks
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2021-10-07 17:05:35 -07:00 |
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tangxifan
|
eddafb42c8
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[Lib] Upgrade parser for fabric key to support shift register banks
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2021-10-07 15:38:42 -07:00 |
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tangxifan
|
a15798a4e1
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[Lib] Upgrade fabric key data structure to support shift register bank definitions
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2021-10-07 14:42:21 -07:00 |
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tangxifan
|
75bd579474
|
Merge pull request #25 from RapidSilicon/qlbank_sr
Now dont' care bits are truelly seen in single-chain and flatten QuickLogic memory bank
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2021-10-07 13:28:36 -07:00 |
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tangxifan
|
9693a269ee
|
[FPGA-Bitstream] Now dont' care bits are truelly seen in single-chain and flatten QuickLogic memory bank
|
2021-10-07 11:31:16 -07:00 |
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tangxifan
|
a464625101
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Merge pull request #24 from RapidSilicon/qlbank_sr
Support custom shift register clock frequency through the simulation setting file
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2021-10-06 17:53:22 -07:00 |
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tangxifan
|
54a8809b3c
|
[FPGA-Verilog] Bug fix in computing clock frequency for shift register chains
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2021-10-06 16:49:28 -07:00 |
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tangxifan
|
8aa2647878
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[Script] Bug fix in slow clock frequency in shift register chain contraints
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2021-10-06 16:49:01 -07:00 |
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tangxifan
|
40b589dc6d
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[Doc] Update documentation about the clock definition for programming clocks in simulation settings
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2021-10-06 13:50:33 -07:00 |
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tangxifan
|
27153bbc89
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[FPGA-Verilog] Bug fix in matching shift register clocks between verilog ports and simulation setting definition
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2021-10-06 13:38:51 -07:00 |
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tangxifan
|
dc5aedc393
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[Script] Correct naming for clocks in shifter register chain defined in simulation setting files
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2021-10-06 13:36:35 -07:00 |
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tangxifan
|
a1eaacf5a8
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[Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency
|
2021-10-06 12:12:15 -07:00 |
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tangxifan
|
554018449e
|
[Test] Update regression test script
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2021-10-06 12:10:37 -07:00 |
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tangxifan
|
b98a8ec718
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[Test] Added the dedicated test case for fixed shift register clock frequency
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2021-10-06 12:09:26 -07:00 |
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tangxifan
|
169bb5fa45
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[Script] Add an example simulation setting file with a fixed clock frequency for shift registers
|
2021-10-06 11:58:50 -07:00 |
|
tangxifan
|
bf473f50f8
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[FPGA-Verilog] Correct bugs in logging clock frequencies
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2021-10-06 11:55:57 -07:00 |
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tangxifan
|
fcb5470baa
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[Lib] Add validator to check if a clock is constrained in simulation settings
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2021-10-06 11:48:23 -07:00 |
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tangxifan
|
82ed6b177b
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[FPGA-Verilog] Now consider clock constraints for BL/WL shift registers
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2021-10-06 11:39:28 -07:00 |
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tangxifan
|
95b877924a
|
Merge pull request #23 from RapidSilicon/qlbank_sr
QuickLogic Memory Bank Now Supports Don't Care Bits in Bitstream file
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2021-10-05 20:45:57 -07:00 |
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tangxifan
|
03bcf6dee5
|
[Doc] Update documenation for the new option ``--keep_dont_care_bits``
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2021-10-05 19:23:42 -07:00 |
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tangxifan
|
189ade6c1e
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[Test] Bug fix
|
2021-10-05 19:17:34 -07:00 |
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tangxifan
|
f74ea5d39a
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[Test] Use the new openfpga shell script in don't care bit tests
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2021-10-05 19:14:44 -07:00 |
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tangxifan
|
4add9781d5
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[Script] Add a new openfpga shell script for don't care bits outputting
|
2021-10-05 19:13:50 -07:00 |
|
tangxifan
|
50604e4589
|
[Test] move test cases
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2021-10-05 19:02:43 -07:00 |
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tangxifan
|
064ac478f3
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[Test] Deploy news test to fpga-bitstream regression tests
|
2021-10-05 19:01:03 -07:00 |
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tangxifan
|
fed6c133b1
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[Test] Add new tests to validate the correctness of bitstream files with don't care bits
|
2021-10-05 18:59:33 -07:00 |
|
tangxifan
|
2ea9826b17
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[FPGA-Bitstream] Bug fix in wrong option name
|
2021-10-05 18:58:47 -07:00 |
|
tangxifan
|
ad54c8547e
|
[FPGA-Bitstream] Added an option to ``write_fabric_bitstream`` command to enable outputting don't care bits in bitstream files
|
2021-10-05 18:54:02 -07:00 |