tangxifan
|
edfa72a666
|
try to fix the bug in clock net identification
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2019-08-13 16:47:28 -06:00 |
|
tangxifan
|
1118b28397
|
use single subckt for switch box again, to abolish the multi-module subckt
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2019-08-13 16:11:04 -06:00 |
|
tangxifan
|
4cffd8ac2d
|
keep route file updated with tileable rr_graph
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2019-08-13 15:37:42 -06:00 |
|
tangxifan
|
c7526cb43c
|
memory sanitized
|
2019-08-13 14:19:40 -06:00 |
|
tangxifan
|
ef4d15df4e
|
reorganize the libarchfpga repository
|
2019-08-13 13:37:35 -06:00 |
|
tangxifan
|
392f579836
|
add linking functions for circuit models and architecture, memory sanitizing is ongoing
|
2019-08-13 13:25:23 -06:00 |
AurelienUoU
|
8dab4dec90
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-08-13 11:09:29 -06:00 |
|
AurelienUoU
|
7851246424
|
Resolve merge issue
|
2019-08-13 11:08:30 -06:00 |
|
tangxifan
|
c56f289d3e
|
add checkers for circuit library
|
2019-08-12 16:45:33 -06:00 |
|
tangxifan
|
d4ae160d3a
|
start adding circuit library checkers
|
2019-08-12 14:20:11 -06:00 |
|
AurelienUoU
|
2da4d3f33c
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-08-12 09:57:02 -06:00 |
|
tangxifan
|
fbdab32a2d
|
timing graph for circuit models are working
|
2019-08-10 13:03:24 -06:00 |
|
tangxifan
|
c004699a14
|
complete parsers for ports
|
2019-08-09 21:00:41 -06:00 |
|
tangxifan
|
2c7d6e3de4
|
adding port parsers
|
2019-08-09 17:48:55 -06:00 |
Ganesh Gore
|
9ab57d1b2e
|
Added fpga_flow script - Working Yosys
|
2019-08-09 16:49:05 -06:00 |
|
tangxifan
|
f80e58c753
|
developing a in-house tokenizer
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2019-08-09 16:36:22 -06:00 |
|
tangxifan
|
3d7adb3dd9
|
start developing parsers for delay values
|
2019-08-09 15:52:28 -06:00 |
|
tangxifan
|
6b5ac2e1ef
|
add timing graph builder for circuit models
|
2019-08-09 12:45:03 -06:00 |
|
Ganesh Gore
|
b82369dd96
|
Added first draft of fpga_task script
|
2019-08-09 00:17:06 -06:00 |
|
tangxifan
|
c8d04c4f00
|
plug in fast look-up builder
|
2019-08-08 21:20:28 -06:00 |
|
Ganesh Gore
|
0cc439f76c
|
Working lattice benchmark unclean commit
|
2019-08-08 18:08:39 -06:00 |
|
tangxifan
|
158c67075e
|
built a conversion from spice_models to circuit_library and plug in
|
2019-08-08 17:25:27 -06:00 |
Baudouin Chauviere
|
0b46adb5ef
|
Correction to the explicit Verilog for FPGAs above 2x2
|
2019-08-08 15:17:43 -06:00 |
|
tangxifan
|
e19485bbb7
|
add more accessors and more to be added when plug into framework
|
2019-08-08 14:16:29 -06:00 |
|
tangxifan
|
ad8c33e1ba
|
complete the mutators
|
2019-08-08 11:33:11 -06:00 |
|
tangxifan
|
5b0c9572c3
|
add mutators for delay_info
|
2019-08-07 21:19:16 -06:00 |
|
tangxifan
|
03a64e2ad8
|
complete the mutators for ports
|
2019-08-07 20:54:27 -06:00 |
|
tangxifan
|
9f8c7a3fc7
|
adding port mutators
|
2019-08-07 17:47:39 -06:00 |
|
tangxifan
|
ed4642a23f
|
adding basic mutators
|
2019-08-07 17:12:05 -06:00 |
|
tangxifan
|
38962c4607
|
adding member functions for circuit library
|
2019-08-07 15:45:27 -06:00 |
|
tangxifan
|
74da4ed51a
|
start creating the class for circuit models
|
2019-08-07 11:38:45 -06:00 |
|
tangxifan
|
f57495feba
|
Now we can also auto-generate the Verilog for a mux2 std cell
|
2019-08-06 15:19:01 -06:00 |
|
tangxifan
|
55bfaf271d
|
Merge branch 'dev' into std_map_support
|
2019-08-06 14:38:19 -06:00 |
|
tangxifan
|
afa468a442
|
hotfix in minor Verilog generation
|
2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
b207050b03
|
minor fix in documentation
|
2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
b4f3dfc82d
|
bug fixing for local encoder's bitstream generation
|
2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
fc93a4941a
|
update documentation
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
7603850d72
|
complete documentation for new features
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
3a490fdd59
|
bug fixing on the port map alignment
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
890ff05628
|
bug fixing and get ready for testing
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
c08c136844
|
set a working range for the encoders
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
386bddacd1
|
updated bitstream generator for local encoders
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
557b1af633
|
add Verilog generation for local encoders, bitstream upgrade TODO
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
003883b13b
|
implementing the local encoders
|
2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
fb2ca66ce9
|
start adding submodules of local encoders to multiplexer
|
2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
33f3a991b5
|
init effort to start developing mux local encoders
|
2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
7748340314
|
hot fix on tutorial
|
2019-08-06 14:17:55 -06:00 |
|
Baudouin Chauviere
|
0a5546e43c
|
Fully functional
|
2019-08-05 14:06:07 -06:00 |
|
tangxifan
|
2291c52fab
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-30 16:54:55 -06:00 |
|
tangxifan
|
8a046394f8
|
add documentation for multi-mode configurable block support
|
2019-07-30 16:47:41 -06:00 |