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Fully functional

This commit is contained in:
Baudouin Chauviere 2019-08-05 14:06:07 -06:00
parent e52deac6ad
commit 0a5546e43c
8 changed files with 70 additions and 54 deletions
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2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c
View File

@ -372,7 +372,7 @@ void dump_verilog_membank_one_inv_module(FILE* fp,
inv_spice_model->name, inv_spice_model->prefix,
instance_tag, inv_index);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, inv_spice_model, FALSE, FALSE, inv_spice_model->dump_explicit_port_map)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, inv_spice_model, FALSE, FALSE, inv_spice_model->dump_explicit_port_map, TRUE)) {
fprintf(fp, ",\n");
}
/* Dump explicit port map if required */

8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
View File

@ -1142,7 +1142,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s_%d_ (", cur_interc->spice_model->prefix, cur_interc->spice_model->cnt);
cur_interc->spice_model->cnt++; /* Stats the number of spice_model used*/
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) {
fprintf(fp, ",\n");
}
/* Print the pin names! Input and output
@ -1278,7 +1278,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s_size%d ", cur_interc->spice_model->name, fan_in);
fprintf(fp, "%s_size%d_%d_ (", cur_interc->spice_model->prefix, fan_in, cur_interc->spice_model->cnt);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) {
fprintf(fp, ",\n");
}
/* Inputs */
@ -1873,7 +1873,9 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
} else {
if (0 < rec_dump_verilog_spice_model_global_ports(fp,
cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model,
FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) {
FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping),
FALSE)) {
fprintf(fp, ",\n");
}
}

20
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
View File

@ -123,7 +123,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "\n");
/* Only dump the global ports belonging to a spice_model
*/
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) {
fprintf(fp, ",\n");
}
@ -228,13 +228,17 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
}
/* Call the subckt*/
fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt);
if (0 == strcmp(verilog_model->name,port_prefix)) {
fprintf(fp, "%s %s_logic_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt);
} else {
fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt);
}
fprintf(fp, "\n");
/* Only dump the global ports belonging to a spice_model
* Disable recursive here !
*/
/*if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {*/
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map, TRUE)) {
fprintf(fp, ",\n");
}
@ -535,7 +539,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
formatted_subckt_prefix, cur_pb_type->name);
fprintf(fp, "\n");
/* Only dump the global ports belonging to a spice_model */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) {
fprintf(fp, ",\n");
}
/* Print inputs, outputs, inouts, clocks, NO SRAMs*/
@ -610,14 +614,18 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
subckt_require_explicit_port_map = TRUE;
}
/* Call LUT subckt*/
fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt);
if (0 == strcmp(verilog_model->name,port_prefix)) {
fprintf(fp, "%s %s_logic_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt);
} else {
fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt);
}
fprintf(fp, "\n");
/* if we have to add global ports when dumping submodules of LUTs
* otherwise, the port map here does not match that of submodules
* Only dump the global ports belonging to a spice_model
* DISABLE recursive here !
*/
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map, TRUE)) {
fprintf(fp, ",\n");
}
/* Connect inputs*/

8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -836,7 +836,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
verilog_model->prefix, mux_size, verilog_model->cnt);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
@ -1093,7 +1093,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
verilog_model->prefix, mux_size, verilog_model->cnt);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) {
fprintf(fp, ",\n");
}
@ -2975,7 +2975,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
verilog_model->prefix, mux_size, verilog_model->cnt);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) {
fprintf(fp, ",\n");
}
@ -3222,7 +3222,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
verilog_model->prefix, mux_size, verilog_model->cnt);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) {
fprintf(fp, ",\n");
}

50
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
View File

@ -642,7 +642,7 @@ void dump_verilog_cmos_mux_one_basis_module(FILE* fp,
/* Print the port list and definition */
fprintf(fp, "module %s (\n", mux_basis_subckt_name);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
/* Port list */
@ -760,7 +760,7 @@ void dump_verilog_cmos_mux_one_basis_module_structural(FILE* fp,
/* Print the port list and definition */
fprintf(fp, "module %s (\n", mux_basis_subckt_name);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
/* Port list */
@ -863,7 +863,7 @@ void dump_verilog_rram_mux_one_basis_module_structural(FILE* fp,
/* Print the port list and definition */
fprintf(fp, "module %s (\n", mux_basis_subckt_name);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
/* Port list */
@ -928,7 +928,7 @@ void dump_verilog_rram_mux_one_basis_module(FILE* fp,
/* Print the port list and definition */
fprintf(fp, "module %s (\n", mux_basis_subckt_name);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
/* Port list */
@ -1264,7 +1264,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp,
}
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(use_explicit_port_map))) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(use_explicit_port_map), TRUE)) {
fprintf(fp, ",\n");
}
if (true == use_explicit_port_map) {
@ -1307,7 +1307,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp,
} else {
assert (SPICE_MODEL_PASSGATE == tgate_spice_model->type);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
@ -1361,7 +1361,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp,
spice_model.lut_intermediate_buffer->spice_model_name,
nextlevel, out_idx); /* Given name*/
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.lut_intermediate_buffer->spice_model, FALSE, FALSE, spice_model.lut_intermediate_buffer->spice_model->dump_explicit_port_map)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.lut_intermediate_buffer->spice_model, FALSE, FALSE, spice_model.lut_intermediate_buffer->spice_model->dump_explicit_port_map, TRUE)) {
fprintf(fp, ",\n");
}
/* Dump explicit port map if required */
@ -1456,7 +1456,7 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp,
/* Print the special basis */
fprintf(fp, "%s special_basis(", mux_special_basis_subckt_name);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
@ -1495,7 +1495,7 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp,
fprintf(fp, "%s ", mux_basis_subckt_name); /* subckt_name */
fprintf(fp, "mux_basis_no%d (", mux_basis_cnt); /* given_name */
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
@ -1561,7 +1561,7 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp,
fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE,
my_bool_to_boolean(is_explicit_mapping))) {
my_bool_to_boolean(is_explicit_mapping), TRUE)) {
fprintf(fp, ",\n");
}
fprintf(fp, "//----- MUX inputs -----\n");
@ -1715,7 +1715,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp,
spice_model.name, mux_size);
fprintf(fp, "module %s_mux(\n", spice_model.name);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
/* Print input ports*/
@ -1797,7 +1797,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp,
spice_model.input_buffer->spice_model_name,
spice_model.input_buffer->spice_model_name, i); /* Given name*/
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) {
fprintf(fp, ",\n");
}
/* Dump explicit port map if required */
@ -1863,7 +1863,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp,
spice_model.output_buffer->spice_model_name,
iport, ipin); /* subckt name */
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) {
fprintf(fp, ",\n");
}
/* check */
@ -1973,7 +1973,7 @@ void dump_verilog_rram_mux_tree_structure(FILE* fp,
/* Each basis mux2to1: <given_name> <input0> <input1> <output> <sram> <sram_inv> svdd sgnd <subckt_name> */
fprintf(fp, "%s mux_basis_no%d (", mux_basis_subckt_name, mux_basis_cnt); /* given_name */
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, nextj); /* input0 input1 */
@ -2052,7 +2052,7 @@ void dump_verilog_rram_mux_multilevel_structure(FILE* fp,
/* Print the special basis */
fprintf(fp, "%s special_basis(\n", mux_special_basis_subckt_name);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* inputs */
@ -2070,7 +2070,7 @@ void dump_verilog_rram_mux_multilevel_structure(FILE* fp,
fprintf(fp, "%s ", mux_basis_subckt_name); /* subckt_name */
fprintf(fp, "mux_basis_no%d (", mux_basis_cnt); /* given_name */
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */
@ -2115,7 +2115,7 @@ void dump_verilog_rram_mux_onelevel_structure(FILE* fp,
fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
fprintf(fp, "//----- MUX inputs -----\n");
@ -2199,7 +2199,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp,
gen_verilog_one_mux_module_name(&spice_model, mux_size));
}
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
/* Print input ports*/
@ -2255,7 +2255,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp,
spice_model.input_buffer->spice_model_name,
spice_model.input_buffer->spice_model_name, i); /* Given name*/
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) {
fprintf(fp, ",\n");
}
/* Dump explicit port map if required */
@ -2318,7 +2318,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp,
spice_model.output_buffer->spice_model_name,
spice_model.output_buffer->spice_model_name); /* subckt name */
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) {
fprintf(fp, ",\n");
}
/* Dump explicit port map if required */
@ -2729,7 +2729,7 @@ void dump_verilog_wire_module(FILE* fp,
/* Add an output at middle point for connecting CB inputs */
fprintf(fp, "module %s (\n", wire_subckt_name);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
fprintf(fp, "input wire %s, output wire %s, output wire mid_out);\n",
@ -2742,7 +2742,7 @@ void dump_verilog_wire_module(FILE* fp,
fprintf(fp, "module %s (\n",
wire_subckt_name);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
fprintf(fp, "input wire %s, output wire %s);\n",
@ -2807,7 +2807,7 @@ void dump_verilog_submodule_one_lut(FILE* fp,
fprintf(fp, "//-----LUT module, verilog_model_name=%s -----\n", verilog_model->name);
fprintf(fp, "module %s (", verilog_model->name);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, FALSE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
/* Print module port list */
@ -3058,7 +3058,7 @@ void dump_verilog_submodule_one_lut(FILE* fp,
verilog_model->lut_input_buffer->spice_model->name,
input_port[0]->prefix, ipin);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_buffer->spice_model, FALSE, FALSE, TRUE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) {
fprintf(fp, ",\n");
}
/* Dump explicit port map if required */
@ -3102,7 +3102,7 @@ void dump_verilog_submodule_one_lut(FILE* fp,
verilog_model->lut_input_inverter->spice_model->name,
input_port[0]->prefix, ipin);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_inverter->spice_model, FALSE, FALSE, TRUE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_inverter->spice_model, FALSE, FALSE, TRUE, TRUE)) {
fprintf(fp, ",\n");
}
/* Dump explicit port map if required */

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c
View File

@ -934,7 +934,7 @@ void dump_verilog_one_clb2clb_direct(FILE* fp,
fprintf(fp, "%s ", cur_direct->spice_model->name);
fprintf(fp, "%s_%d_ (", cur_direct->spice_model->prefix, cur_direct->spice_model->cnt);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_direct->spice_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_direct->spice_model, FALSE, FALSE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
/* Input: Print the source grid pin */

31
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
View File

@ -852,7 +852,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp,
const t_spice_model* cur_spice_model,
boolean dump_port_type,
boolean recursive,
boolean require_explicit_port_map) {
boolean require_explicit_port_map,
boolean is_lib_name) {
int dumped_port_cnt;
boolean dump_comma = FALSE;
t_spice_model_port* cur_spice_model_port = NULL;
@ -901,9 +902,13 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp,
} else {
/* Add explicit port mapping if required */
if (TRUE == require_explicit_port_map ) {
fprintf(fp, ".%s(",
cur_spice_model_port->lib_name);
//cur_spice_model_port->prefix);
if (TRUE == is_lib_name) {
fprintf(fp, ".%s(",
cur_spice_model_port->lib_name);
} else {
fprintf(fp, ".%s(",
cur_spice_model_port->prefix);
}
}
fprintf(fp, "%s[0:%d]",
cur_spice_model_port->prefix,
@ -1861,7 +1866,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i
fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix,
cur_sram_verilog_model->cnt);
/* Only dump the global ports belonging to a spice_model */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
@ -1914,7 +1919,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i
fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix,
cur_sram_verilog_model->cnt);
/* Only dump the global ports belonging to a spice_model */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Input*/
@ -1931,7 +1936,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i
fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix,
cur_sram_verilog_model->cnt);
/* Only dump the global ports belonging to a spice_model */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
/* Input of Scan-chain DFF, should be connected to the output of its precedent */
@ -2027,7 +2032,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix,
cur_sram_verilog_model->cnt);
/* Only dump the global ports belonging to a spice_model */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_num_sram); /* Input*/
@ -2067,7 +2072,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix,
cur_sram_verilog_model->cnt);
/* Only dump the global ports belonging to a spice_model */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Input*/
@ -2084,7 +2089,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix,
cur_sram_verilog_model->cnt);
/* Only dump the global ports belonging to a spice_model */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) {
fprintf(fp, ",\n");
}
/* Input of Scan-chain DFF, should be connected to the output of its precedent */
@ -3047,7 +3052,7 @@ void dump_verilog_mem_module_port_map(FILE* fp,
* Other ports are not accepted!!!
*/
/* 1. Global ports! */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, mem_model, dump_port_type, TRUE, require_explicit_port_map)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, mem_model, dump_port_type, TRUE, require_explicit_port_map, TRUE)) {
dump_first_comma = TRUE;
}
@ -3164,7 +3169,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
}
/* Only dump the global ports belonging to a spice_model */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) {
fprintf(fp, ",\n");
}
@ -3212,7 +3217,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
case SPICE_SRAM_STANDALONE:
/* SRAM subckts*/
/* Only dump the global ports belonging to a spice_model */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) {
fprintf(fp, ",\n");
}
fprintf(fp, "%s_in[%d:%d], ",

3
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h
View File

@ -73,7 +73,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp,
const t_spice_model* cur_spice_model,
boolean dump_port_type,
boolean recursive,
boolean require_explicit_port_map);
boolean require_explicit_port_map,
boolean is_lib_name);
int dump_verilog_global_ports(FILE* fp, t_llist* head,
boolean dump_port_type,