tangxifan
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1cfc117b32
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developed verilog instance writer. refactoring on mux ongoing
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2019-08-25 15:47:57 -06:00 |
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tangxifan
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056c45321b
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plug in module manager
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2019-08-25 15:44:31 -06:00 |
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tangxifan
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8fc258cc93
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develop and plug mux_lib_builder, refactoring the mux submodule generation
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2019-08-25 15:33:37 -06:00 |
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tangxifan
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c43fabb43c
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developed verilog instance writer. refactoring on mux ongoing
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2019-08-25 10:31:45 -06:00 |
Ganesh Gore
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7a3ff94116
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Added blif task in travis script
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2019-08-25 01:28:21 -06:00 |
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Ganesh Gore
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937ebd1b85
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-08-25 00:53:18 -06:00 |
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Ganesh Gore
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c4180fad6d
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Added .gitignore to build docs locally
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2019-08-25 00:49:04 -06:00 |
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Ganesh Gore
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632c9d6976
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Added python execution path in config file
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2019-08-25 00:42:48 -06:00 |
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Ganesh Gore
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f558437ae1
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Added task for vpr_blif flow
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2019-08-25 00:23:39 -06:00 |
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tangxifan
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fe7dfd59c3
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Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-08-24 23:54:37 -06:00 |
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tangxifan
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63f40f48fa
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develop and plug mux_lib_builder, refactoring the mux submodule generation
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2019-08-24 19:23:33 -06:00 |
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tangxifan
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27b619554d
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add stats for verilog modules
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2019-08-23 20:23:42 -06:00 |
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tangxifan
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ad06e9c98c
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plug in module manager
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2019-08-23 20:23:41 -06:00 |
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tangxifan
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39853408dd
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add recursive global port searching for circuit library
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2019-08-23 20:23:41 -06:00 |
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tangxifan
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fcb31e4c24
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add stats for verilog modules
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2019-08-23 18:41:16 -06:00 |
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tangxifan
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8eebca9daa
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plug in module manager
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2019-08-23 17:39:29 -06:00 |
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tangxifan
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1b4de2b335
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Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-08-23 16:37:24 -06:00 |
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tangxifan
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37a092e885
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add recursive global port searching for circuit library
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2019-08-23 16:36:30 -06:00 |
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Ganesh Gore
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2e3f906d40
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Solved bug in travis script file
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2019-08-23 16:03:21 -06:00 |
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tangxifan
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3fb3082447
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add more tests
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2019-08-23 14:10:01 -06:00 |
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tangxifan
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e55c6d5b41
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add more tests
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2019-08-23 14:09:20 -06:00 |
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tangxifan
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95f8fea299
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-08-23 13:45:30 -06:00 |
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tangxifan
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ede29aa656
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Merge branch 'refactoring' into dev
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2019-08-23 13:42:10 -06:00 |
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Ganesh Gore
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52d6a9e979
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-08-23 13:41:29 -06:00 |
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tangxifan
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931b042750
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refactoring module manager
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2019-08-23 12:52:01 -06:00 |
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Ganesh Gore
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82a186bf7c
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Added python3.5 in travis script
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2019-08-23 12:45:17 -06:00 |
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Ganesh Gore
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28dde899db
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Updated Architecture Template
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2019-08-23 12:44:45 -06:00 |
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tangxifan
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520630c5e2
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add more testing tasks
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2019-08-23 10:16:52 -06:00 |
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tangxifan
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732e24767f
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developing module manager
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2019-08-22 23:49:35 -06:00 |
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Ganesh Gore
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6e7de16ad4
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Solved bug in commnad rearrangement
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2019-08-22 23:41:25 -06:00 |
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Ganesh Gore
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89589ddc1c
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-08-22 18:46:51 -06:00 |
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Ganesh Gore
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4189ada1eb
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Fixed run test file
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2019-08-22 17:31:46 -06:00 |
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Ganesh Gore
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5027f9c4b3
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Added test mode script in travis
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2019-08-22 17:03:56 -06:00 |
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Ganesh Gore
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8f80cb3c24
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Added Sample script to run blif VPR
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2019-08-22 17:02:12 -06:00 |
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Ganesh Gore
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77e2a7bca3
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Added execution time logs in flow script
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2019-08-22 17:01:38 -06:00 |
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Ganesh Gore
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30cbe38d3d
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Added Test Modes - Added blif VPR Option
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2019-08-22 17:00:59 -06:00 |
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Ganesh Gore
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d5ce1b557e
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Made thread logs prettier
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2019-08-22 16:56:58 -06:00 |
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tangxifan
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3f45e6cc87
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remove dead codes for essential gates code generation
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2019-08-22 10:01:52 -06:00 |
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tangxifan
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43de2d7636
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some tuning on Verilog port formatting
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2019-08-21 23:47:50 -06:00 |
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tangxifan
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1be5632e92
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minor tuning on the delay assignment
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2019-08-21 23:11:54 -06:00 |
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tangxifan
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7b0c55ce15
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try to reduce precision in timing assignment of Verilog netlist (travis iverilog was not happy)
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2019-08-21 22:45:48 -06:00 |
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tangxifan
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5a40c6713d
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managed to plug in refactored essential gates, dead codes to be removed
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2019-08-21 21:50:26 -06:00 |
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tangxifan
|
d8eb9866a0
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refactored gate verilog generation
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2019-08-21 18:49:48 -06:00 |
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tangxifan
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b08ff465c9
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refactored pass-gate verilog generation
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2019-08-21 17:33:16 -06:00 |
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tangxifan
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1a15b9efd4
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update travis settings
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2019-08-21 15:27:07 -06:00 |
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tangxifan
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5e156dc725
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minor fix for OSX and update travis using ccache to speed up compilation
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2019-08-21 15:25:36 -06:00 |
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tangxifan
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42b528be57
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doc updates
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2019-08-21 15:11:25 -06:00 |
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tangxifan
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9c43b1b753
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complete refacotriing the inv and buf part in submodules
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2019-08-21 14:54:05 -06:00 |
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Ganesh Gore
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764d7039b5
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Import utils bug fixing for travis test
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2019-08-21 12:42:58 -06:00 |
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Ganesh Gore
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2f0acfad23
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Updated travis to run regression task
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2019-08-21 11:09:53 -06:00 |