tangxifan
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49bfb3223c
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add compact routing to regression test
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2019-11-01 10:53:47 -06:00 |
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tangxifan
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139ea8b3e3
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add s298 single mode arch to Travis
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2019-11-01 10:49:37 -06:00 |
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tangxifan
|
531cc064fc
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bug fixing for formal top-level testbench
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2019-11-01 10:47:40 -06:00 |
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tangxifan
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d709868463
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adding more regression tests which is quick run but very helpful for debugging
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2019-10-31 20:17:40 -06:00 |
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tangxifan
|
2dff779005
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critical bug fixed for bitstream generation for offset truth tables
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2019-10-31 20:16:08 -06:00 |
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tangxifan
|
a6a3e7c36b
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adding mcnc_big20 to regression test
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2019-10-31 19:31:27 -06:00 |
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tangxifan
|
de78718724
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remove unused gcc setting in travis
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2019-10-30 20:07:32 -06:00 |
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tangxifan
|
7eac8be475
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try to upgrade travis OS linux for the latest iverilog
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2019-10-30 20:04:20 -06:00 |
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tangxifan
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858c1aefce
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try use force for Icarus
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2019-10-30 19:50:34 -06:00 |
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tangxifan
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5531422186
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update regression test with no-explicit port mapping cases
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2019-10-30 19:37:06 -06:00 |
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tangxifan
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7460dc8cab
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pass current regression tests
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2019-10-30 19:10:36 -06:00 |
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tangxifan
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55fbd72293
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many bugs have been fixed
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2019-10-30 15:50:42 -06:00 |
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tangxifan
|
4398cffaaa
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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tangxifan
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1faacfa3cf
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keep autocheck testbenches underwater now, bring them back when refactored. Start plugging in the new engine
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2019-10-29 14:23:09 -06:00 |
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tangxifan
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7c116aac2f
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added Verilog generation for preconfig top module
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2019-10-29 13:54:35 -06:00 |
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tangxifan
|
10491c4291
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bring single mode test case online with bug fixing
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2019-10-28 17:04:10 -06:00 |
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tangxifan
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5cb3717433
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add single mode test case to regression test. debugging now
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2019-10-28 15:57:17 -06:00 |
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tangxifan
|
fe005f1f56
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remove legacy codes for Verilog formal verification testbench generation
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2019-10-28 15:21:14 -06:00 |
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tangxifan
|
c047fd3cb2
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plugged in the refactored formal verification Verilog testbench using random vectors
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2019-10-28 15:10:29 -06:00 |
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tangxifan
|
ccabe4ce2a
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refactoring Verilog formal verification top testbench using random vectors
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2019-10-28 14:45:51 -06:00 |
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tangxifan
|
55eea6c4d5
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rename files to be clear
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2019-10-27 20:12:48 -06:00 |
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tangxifan
|
35073f48cf
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add runtime profiling to module graph builders
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2019-10-27 19:10:21 -06:00 |
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tangxifan
|
2b06cfc3cf
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added fabric bitstream generator and fixed critical bugs in top module graph
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2019-10-27 18:47:33 -06:00 |
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tangxifan
|
f116351831
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add instance name for each pb graph node
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2019-10-26 17:25:45 -06:00 |
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tangxifan
|
7649d9228e
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fixed bugs in refactored bitstream generation
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2019-10-26 16:40:14 -06:00 |
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tangxifan
|
0a9c89be0b
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add bitstream writers and start debugging
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2019-10-26 12:41:23 -06:00 |
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tangxifan
|
ca2b836128
|
temporary remove MacOS from travis. Will bring back when debugged
|
2019-10-25 22:13:48 -06:00 |
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tangxifan
|
db9beec77c
|
try to fix Travis MacOS issue
|
2019-10-25 21:52:30 -06:00 |
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tangxifan
|
3310bac65b
|
refactored grid bitstream generation
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2019-10-25 21:49:47 -06:00 |
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tangxifan
|
fc2562fc6c
|
change travis to an older version of XCode/MacOS but rather stable
|
2019-10-25 13:08:10 -06:00 |
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tangxifan
|
4b7a9dfa63
|
add instance name correlation between module and bitstream generation
|
2019-10-25 13:06:48 -06:00 |
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tangxifan
|
cb147c1180
|
try to fix MacOS in travisCI
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2019-10-25 10:44:40 -06:00 |
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tangxifan
|
0b687669c8
|
affliate configuration bitstream to sb blocks
|
2019-10-25 10:42:12 -06:00 |
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tangxifan
|
cc63adf6e0
|
bring back MacOS header file package installation in Travis
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2019-10-25 09:36:36 -06:00 |
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tangxifan
|
1ee7dd80b2
|
remove MacOS header file installation
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2019-10-24 22:52:08 -06:00 |
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tangxifan
|
a1cd1ea8b4
|
fix travis error for MacOS
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2019-10-24 22:51:24 -06:00 |
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tangxifan
|
c38513c838
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add local encoder support in bitstream generation refactoring
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2019-10-24 22:49:24 -06:00 |
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tangxifan
|
97193794c4
|
correct bugs in organizing child modules in top-level module
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2019-10-24 21:27:42 -06:00 |
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tangxifan
|
838173f3c4
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start refactoring bitstream generator
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2019-10-24 21:01:11 -06:00 |
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tangxifan
|
13c62fdcf8
|
add more methods to bitstream manager (renamed from bitstream context)
|
2019-10-24 15:43:29 -06:00 |
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tangxifan
|
f26dbfe080
|
add instance name for top-level modules to ease readability
|
2019-10-23 20:24:52 -06:00 |
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tangxifan
|
2787a07f0d
|
start refactoring bitstream generation
|
2019-10-23 17:34:21 -06:00 |
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tangxifan
|
a18f1305cd
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add configurable child list to module manager
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2019-10-23 15:44:13 -06:00 |
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tangxifan
|
12162a02bc
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critical bug fixing for compact routing hierarchy and top module generation
|
2019-10-23 14:20:04 -06:00 |
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tangxifan
|
fb2f003d5b
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add top module generation and refactored verilog generation for top module
|
2019-10-23 12:16:58 -06:00 |
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tangxifan
|
dafab3907e
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refactored routing module generation and verilog writing
|
2019-10-23 11:46:55 -06:00 |
|
tangxifan
|
89c8d089a3
|
add grid module generation
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2019-10-22 16:14:11 -06:00 |
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tangxifan
|
9cf8683acd
|
add module generation for memories
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2019-10-22 15:31:08 -06:00 |
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tangxifan
|
3cf7950bc1
|
add wire module generation and simplify Verilog generation for wires
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2019-10-21 20:20:34 -06:00 |
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tangxifan
|
c076da9bab
|
remove redundant codes
|
2019-10-21 18:48:34 -06:00 |