tangxifan
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7e82c23f52
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now add SDC generator supports both hierarchical and flatten in writing timing constraints
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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d0793d9029
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now disable_sb_output support wildcard
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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8695c5ee78
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add options to use general-purpose wildcards in SDC generator
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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e811f8bb21
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plug in netlist manager and now the include_netlist appears in one unique file
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2020-04-23 20:42:11 -06:00 |
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tangxifan
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87b17fc25f
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add netlist manager data structure
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2020-04-23 18:59:09 -06:00 |
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tangxifan
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68b7991a46
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bug fixed for sdc on memory blocks
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2020-04-21 13:37:56 -06:00 |
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tangxifan
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d325bede68
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add fabric bitstream writer
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2020-04-21 12:02:10 -06:00 |
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tangxifan
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e10cafe0a5
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Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
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2020-04-19 16:42:31 -06:00 |
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tangxifan
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b9dab2baaf
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add exit codes to command execution in shell context
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2020-04-08 16:18:05 -06:00 |
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tangxifan
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1fb37f4c71
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improve directory creator to support same functionality as 'mkdir -p'
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2020-04-08 12:55:09 -06:00 |
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tangxifan
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cbcd1d20d4
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fixed memory leakage in pb_pin fixup
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2020-04-07 16:24:04 -06:00 |
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tangxifan
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5a04da2082
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fix memory leakage in openfpga title
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2020-04-07 16:14:41 -06:00 |
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tangxifan
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bcb86801fa
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bug fixed in gpio naming for module manager ports
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2020-04-05 17:26:44 -06:00 |
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tangxifan
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e601a648cc
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relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
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2020-03-27 19:07:34 -06:00 |
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tangxifan
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7c9c2451f2
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debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
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2020-03-27 16:03:42 -06:00 |
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tangxifan
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329b0a9cf1
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add options to enable SDC constraints on zero-delay paths
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2020-03-25 15:55:30 -06:00 |
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tangxifan
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c2e5d6b8e2
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add options to dsiable SDC for non-clock global ports
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2020-03-25 14:38:13 -06:00 |
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tangxifan
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787dc8ce83
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added ASCII OpenFPGA logo in shell interface
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2020-03-25 11:16:04 -06:00 |
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tangxifan
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9e4e12aae9
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fixed echo message in the compression rate of gsb uniquifying
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2020-03-22 16:13:04 -06:00 |
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tangxifan
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ff474d87de
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fixed critical bug in uniquifying GSBs. Now it can guarantee minimum number of unique GSBs
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2020-03-22 16:11:00 -06:00 |
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tangxifan
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3958ac2494
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fix bugs in flow manager on default compress routing problems
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2020-03-22 15:26:15 -06:00 |
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tangxifan
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7b9384f3b2
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add write_gsb command to shell interface
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2020-03-21 19:40:26 -06:00 |
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tangxifan
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9a518e8bb6
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bug fixed for tileable rr_graph builder for more 4x4 fabrics
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2020-03-21 18:07:00 -06:00 |
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tangxifan
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c0e8d98c6f
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bug fixed in tile direct builder
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2020-03-21 12:43:56 -06:00 |
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tangxifan
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aff73bdd74
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deployed edge sorting and make it as an option to link_arch command
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2020-03-08 15:59:53 -06:00 |
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tangxifan
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37423729ec
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bug fixing for naming the duplicated pins
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2020-03-07 15:44:57 -07:00 |
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tangxifan
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7fcd27e000
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now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
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2020-03-03 12:29:58 -07:00 |
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tangxifan
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3241d8bd37
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put analysis sdc writer online. Minor bug in redudant '/' to be fixed
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2020-03-02 19:54:18 -07:00 |
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tangxifan
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037c7e5c43
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adapt top-level function for analysis SDC writer
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2020-03-02 17:58:44 -07:00 |
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tangxifan
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a17c14c363
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clean-up command addition and add fabric bitstream building to sample script
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2020-03-02 10:39:19 -07:00 |
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tangxifan
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aa66042dfb
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move simulation setting annotation to a separated source file
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2020-02-29 15:19:02 -07:00 |
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tangxifan
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7b18f7cd09
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now the auto select number of clocks in simulation is online
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2020-02-29 13:29:16 -07:00 |
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tangxifan
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542fadaaae
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allow users to use VPR critical path delay in OpenFPGA simulation
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2020-02-28 12:10:27 -07:00 |
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tangxifan
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de8425874c
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use user defined critical path delay in SDC generation
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2020-02-28 11:24:39 -07:00 |
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tangxifan
|
092e10afda
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bring pnr sdc generator online and fixed minor bugs in bitstream writing
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2020-02-28 11:14:50 -07:00 |
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tangxifan
|
9b769cd8e4
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bug fix for using renamed i/o names
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2020-02-27 16:37:20 -07:00 |
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tangxifan
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078f72320f
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debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports
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2020-02-27 13:24:26 -07:00 |
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tangxifan
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f558405887
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ported verilog testbench generator online. Split from fabric generator. Testing to be done
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2020-02-27 12:33:09 -07:00 |
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tangxifan
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b3796b0818
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build io location map
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2020-02-26 19:58:18 -07:00 |
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tangxifan
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25e0583636
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add io location map data structure and start porting verilog testbench generator
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2020-02-26 17:10:57 -07:00 |
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tangxifan
|
a26d31b87f
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make write bitstream online
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2020-02-26 11:09:23 -07:00 |
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tangxifan
|
4024ed63cb
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add truth table build up for physical LUTs
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2020-02-25 22:39:42 -07:00 |
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tangxifan
|
8e9660b816
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add mapped block fast look-up as placement annotation
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2020-02-24 16:09:29 -07:00 |
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tangxifan
|
2d17395e13
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start integrating fpga_bitstream. Bring data structures online
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2020-02-22 23:04:42 -07:00 |
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tangxifan
|
4abaef14b5
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bug fixed in pb_pin fix-up. This is due to A CRITICAL BUG IN PHYSICAL_TILE PIN MAPPING!!!
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2020-02-20 20:50:59 -07:00 |
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tangxifan
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3e07d7d5e0
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finish net addition to LbRouter. Found a bug in pb pin fix-up. Need to consider clustered I/O block z offset
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2020-02-20 20:26:20 -07:00 |
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tangxifan
|
fdb27c5a6b
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move lb_rr_graph construction to repack command
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2020-02-20 13:24:34 -07:00 |
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tangxifan
|
409b3f6896
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add lb_rr_graph builder for the refactored version
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2020-02-17 21:11:56 -07:00 |
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tangxifan
|
8e97443410
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start working on repack
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2020-02-17 17:57:43 -07:00 |
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tangxifan
|
62e4f14e30
|
add lb_rr_graph to device annotation
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2020-02-17 17:26:27 -07:00 |