tangxifan
|
0f87ae9886
|
support switch block submodule Verilog generation by segments
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2019-06-05 12:56:05 -06:00 |
AurelienUoU
|
84fabbd43b
|
Fix sdc analysis bug related to virtual nodes + add the option in regression test
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2019-06-05 12:10:28 -06:00 |
Baudouin Chauviere
|
d24488092d
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Fix bug
|
2019-06-05 11:40:04 -06:00 |
|
tangxifan
|
c2d8fa00ba
|
add rr_block unique_side_module verilog generation
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2019-06-04 17:47:40 -06:00 |
|
Baudouin Chauviere
|
1932d00309
|
Correction of the SDC to remove global clocks
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2019-05-30 15:04:21 -06:00 |
|
Baudouin Chauviere
|
3da216f297
|
correction Null issue for the flat model
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2019-05-28 14:15:24 -06:00 |
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tangxifan
|
eece161d58
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keep debugging on Switch Block rotation
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2019-05-27 21:10:30 -06:00 |
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tangxifan
|
02b48d036d
|
clean warnings
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2019-05-24 16:48:08 -06:00 |
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tangxifan
|
2c46da6888
|
clean-up warnings Verilog routing generator
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2019-05-24 16:29:17 -06:00 |
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tangxifan
|
27b996337a
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fixed a critical bug in Compact Verilog generation for SB/CBs
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2019-05-24 16:14:46 -06:00 |
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tangxifan
|
1ade1f1d3f
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update SDC generator disabled_unused_mux by using RRSwitchBlock
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2019-05-24 15:42:00 -06:00 |
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tangxifan
|
f27b88db8d
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Use RRChan in SDC generator to replace old data structures
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2019-05-24 15:34:56 -06:00 |
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tangxifan
|
27c234711e
|
clean up warnings in SDC pb_type generator
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2019-05-24 15:23:38 -06:00 |
|
tangxifan
|
924136e7a2
|
Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info
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2019-05-24 15:10:08 -06:00 |
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tangxifan
|
994b90ae53
|
updated report_timing for using RRSwitchBlock
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2019-05-24 14:25:51 -06:00 |
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tangxifan
|
eef1312325
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updated bitstream to use new RRSwitchBlock as well as the report timing engine
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2019-05-24 12:54:10 -06:00 |
|
tangxifan
|
8f4f590ff9
|
update Verilog compact_netlist outputter with RRSwitchBlock classes
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2019-05-23 21:52:12 -06:00 |
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tangxifan
|
ea8c36ce6e
|
upgrade Verilog SB generator using the RRSwitchBlock
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2019-05-23 17:37:39 -06:00 |
|
tangxifan
|
b185a17359
|
add routing_channel unique module generation
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2019-05-20 22:33:17 -06:00 |
giacomin
|
ceee28226e
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-20 16:47:07 -06:00 |
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giacomin
|
8b520349e7
|
fixed a bug for rram based fpga when using explicit verilog port mapping
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2019-05-20 16:44:47 -06:00 |
|
AurelienUoU
|
99beeb48cc
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-13 16:42:27 -06:00 |
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AurelienUoU
|
a3656dde45
|
Add missing Verilog source, Archictecture folder and Testbenches correction
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2019-05-13 16:41:35 -06:00 |
|
Baudouin Chauviere
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b48a27acf0
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-13 14:45:57 -06:00 |
|
Baudouin Chauviere
|
2019840d7c
|
cleaned unused variables
|
2019-05-13 14:45:02 -06:00 |
|
AurelienUoU
|
9c05a4fb0a
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-10 14:09:23 -06:00 |
|
AurelienUoU
|
ff9b84d800
|
Bug fix in Icarus requirement
|
2019-05-10 14:07:32 -06:00 |
|
tangxifan
|
be4643b8a6
|
updated Verilog generator to use compact CBs and SBs. SPICE generator to be updated
|
2019-05-10 10:21:06 -06:00 |
|
Baudouin Chauviere
|
4f386de2ef
|
gen_xxx functions create mem-leaks because the mem is dynamically allocated inside and not freed. TBD later everywhere
|
2019-05-06 17:25:29 -06:00 |
|
Baudouin Chauviere
|
3b62f8e024
|
Conversion from s to ns for the loop breaking delays
|
2019-05-06 16:12:30 -06:00 |
|
Baudouin Chauviere
|
a5a1a376ab
|
Modified code for cleaner delay naming convention
|
2019-05-06 12:52:49 -06:00 |
|
Baudouin Chauviere
|
7860042276
|
added before after loop breaker constraining
|
2019-05-03 14:00:06 -06:00 |
|
Baudouin Chauviere
|
4e330ee463
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-03 10:43:22 -06:00 |
|
Baudouin Chauviere
|
921b694400
|
Bug fix sdc breaking loop of edges outside current interconnect
|
2019-05-03 10:42:35 -06:00 |
|
AurelienUoU
|
42f20eda60
|
Add the user matching for internal register in formal verification script generation
|
2019-05-03 10:24:02 -06:00 |
|
Baudouin Chauviere
|
1ab4688339
|
Create no segment constraint in loop_breaker if none is given by user
|
2019-04-30 12:30:07 -06:00 |
|
tangxifan
|
c46c0fc97d
|
bug fixing for SDC generator
|
2019-04-26 14:07:44 -06:00 |
|
tangxifan
|
46d44fa42a
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |