tangxifan
|
44301bfd77
|
updated SPICE generator to avoid issues on clb2clb_direct
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2019-07-02 09:01:52 -06:00 |
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tangxifan
|
5b25bbb120
|
bug fixed for direct connection in CBs and direct connection in top netlist
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2019-07-01 17:25:00 -06:00 |
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tangxifan
|
1332ba62e8
|
update tileable rr_graph generator to improve routability and also enable assoicated testing
|
2019-06-27 17:52:25 -06:00 |
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tangxifan
|
15c536e9b4
|
minor fixing in printing the rr_node stats
|
2019-06-27 16:34:21 -06:00 |
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tangxifan
|
8edd85c9fc
|
keep fixing bugs in verilog SDC generator for tileable CBs
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2019-06-26 22:58:52 -06:00 |
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tangxifan
|
711e369fe7
|
fixing bugs in the SDC generator and report_timing
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2019-06-26 18:09:09 -06:00 |
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tangxifan
|
0fe54d87d5
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fixed a bug in SDC generator for constraining SBs in tileable arch
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2019-06-26 17:06:14 -06:00 |
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tangxifan
|
7d85eb544d
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start fixing bugs for SDC generator when using tileable arch
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2019-06-26 16:48:17 -06:00 |
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tangxifan
|
f5920c7422
|
fix bugs in ptc_num using for SB
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2019-06-26 16:21:02 -06:00 |
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tangxifan
|
3d8200e217
|
critical bug fixed in bitstream generator for compact routing hierarchy
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2019-06-26 15:51:11 -06:00 |
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tangxifan
|
d2ed82d14d
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Merge branch 'tileable_routing' into multimode_clb
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2019-06-26 15:00:39 -06:00 |
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tangxifan
|
57616361c2
|
fixed critical bugs in cb configuration port indices
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2019-06-26 14:58:52 -06:00 |
Baudouin Chauviere
|
d2bd2be76b
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Warnings correction in the make sequence
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2019-06-26 14:33:12 -06:00 |
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tangxifan
|
42f85004b6
|
fix bugs in finding the ending SB of a rr_node
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2019-06-26 14:13:41 -06:00 |
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tangxifan
|
9b6a4b39bb
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Merge branch 'tileable_routing' into multimode_clb
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2019-06-26 11:36:08 -06:00 |
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tangxifan
|
c879e7f6c5
|
fixed a critical bug when instanciating Connection blocks
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2019-06-26 11:33:02 -06:00 |
|
Baudouin Chauviere
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b7c2954b91
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-06-26 10:51:55 -06:00 |
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Baudouin Chauviere
|
8f21a3b177
|
Memory leakage correction
|
2019-06-26 10:50:38 -06:00 |
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tangxifan
|
d50fb7ee19
|
fixed the bug in determine passing wires for rr_gsb
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2019-06-26 10:50:23 -06:00 |
AurelienUoU
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ec504049ef
|
Update Testbenches to increase accuracy + commented compact routing option until debug
|
2019-06-26 10:01:12 -06:00 |
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tangxifan
|
a3670bb752
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Merge branch 'multimode_clb' into tileable_routing
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2019-06-26 09:45:04 -06:00 |
|
Baudouin Chauviere
|
56557b94e7
|
Bug Fix
|
2019-06-26 08:53:46 -06:00 |
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tangxifan
|
3c0ef2067d
|
fixed critical bugs in pass_tracks identification and update regression test for tileable arch
|
2019-06-25 21:59:38 -06:00 |
|
Baudouin Chauviere
|
bb250ddef9
|
Bug fix in cpp
|
2019-06-25 16:47:10 -06:00 |
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tangxifan
|
4d3b5f12b4
|
fixed bugs for UNIVERSAL and WILTON switch blocks
|
2019-06-25 14:15:29 -06:00 |
|
Baudouin Chauviere
|
332ce17f03
|
Division between horizontal and vertical analysis
|
2019-06-25 13:44:41 -06:00 |
|
tangxifan
|
a88263a4c2
|
update rr_block writer to include IPINs in XML files
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2019-06-25 11:17:22 -06:00 |
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tangxifan
|
785b560bd5
|
sorted drive_rr_nodes for RR GSBs, #. of SBs should be constant now
|
2019-06-24 22:46:56 -06:00 |
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tangxifan
|
fd301eeb66
|
many bug fixing and now start improving the routability of tileable rr_graph
|
2019-06-24 17:33:29 -06:00 |
|
tangxifan
|
0d62661c71
|
bug fixing and spot critical bugs in directlist parser
|
2019-06-23 20:52:38 -06:00 |
|
tangxifan
|
cdd4af9c58
|
vpr likes the tileable rr_graph while fpga_x2p does not
|
2019-06-23 18:11:13 -06:00 |
|
tangxifan
|
59df305668
|
bug fixing and reorganize rr_graph builder source files
|
2019-06-23 16:40:13 -06:00 |
|
tangxifan
|
2837f44df2
|
bug fixing for tileable rr_graph generator.
|
2019-06-22 20:41:06 -06:00 |
|
tangxifan
|
7c38b32eb1
|
keep bug fixing for tileable rr_graph generator
|
2019-06-21 22:51:11 -06:00 |
|
tangxifan
|
1b91c32121
|
Merge branch 'multimode_clb' into tileable_routing
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2019-06-21 17:59:55 -06:00 |
|
tangxifan
|
41954056ce
|
many bug fixing for tileable rr_graph generator. Still debugging
|
2019-06-21 17:58:46 -06:00 |
|
AurelienUoU
|
0a42f6a796
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-06-21 15:47:14 -06:00 |
|
AurelienUoU
|
c0d7099cd6
|
Allow CB on top of blocks with height > 1
|
2019-06-21 15:46:05 -06:00 |
|
tangxifan
|
d48fd959a9
|
keep bug fixing for tileable rr_graph generator
|
2019-06-20 22:30:26 -06:00 |
|
tangxifan
|
548242b368
|
plug-in tileable rr generator which can be enable by a XML property
|
2019-06-20 21:06:26 -06:00 |
|
tangxifan
|
cf82d87e11
|
Merge branch 'multimode_clb' into tileable_routing
|
2019-06-20 18:18:20 -06:00 |
|
tangxifan
|
baab9c4a21
|
basically finished the coding of tileable rr_graph generator. testing to go
|
2019-06-20 18:17:07 -06:00 |
|
Baudouin Chauviere
|
be25b6dd66
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-06-20 14:11:03 -06:00 |
|
Baudouin Chauviere
|
3bd6c40a10
|
Report timing modified to have only one liners
|
2019-06-20 14:10:39 -06:00 |
|
AurelienUoU
|
a7502bb43b
|
Avoid configuration bits for module wihch don't require them
|
2019-06-20 09:40:41 -06:00 |
|
tangxifan
|
e7f2bd3b7c
|
Merge branch 'multimode_clb' into tileable_routing
|
2019-06-19 21:31:54 -06:00 |
|
tangxifan
|
2f15d2d13c
|
keep developing tileable rr_graph, track2ipin and opin2track to go
|
2019-06-19 21:30:16 -06:00 |
|
AurelienUoU
|
ff00e4c79c
|
Free only if it's possible to free
|
2019-06-19 16:15:30 -06:00 |
|
tangxifan
|
ba15358564
|
developing ipin2track mapping for tiles
|
2019-06-18 18:06:21 -06:00 |
|
tangxifan
|
9ca1b42f4c
|
developing switch block pattern for tileable routing architecture
|
2019-06-18 16:52:42 -06:00 |