Baudouin Chauviere
|
01ff484158
|
Explicit verilog passing all tests
|
2019-10-02 10:22:28 -06:00 |
|
Baudouin Chauviere
|
6b3e1fd410
|
Get backup verilog_routing.c
|
2019-10-02 08:54:56 -06:00 |
|
Baudouin Chauviere
|
829cbcfbe3
|
Merge
Merge remote-tracking branch 'origin' into explicit_verilog
|
2019-10-01 16:54:27 -06:00 |
|
Baudouin Chauviere
|
33e50bbc8c
|
fix
|
2019-10-01 16:54:16 -06:00 |
|
Baudouin Chauviere
|
7c3ab38410
|
Hot fix
|
2019-10-01 16:40:16 -06:00 |
|
Baudouin Chauviere
|
633a12ee08
|
Buggy version but need help on debugging
|
2019-10-01 14:49:42 -06:00 |
AurelienUoU
|
36f7624b95
|
Point to point truth table typo fix
|
2019-10-01 13:07:27 -06:00 |
|
AurelienUoU
|
e2867019e1
|
Typo fixing
|
2019-09-30 10:38:02 -06:00 |
|
AurelienUoU
|
74f7a3cfb2
|
Doc fixing
|
2019-09-30 10:29:42 -06:00 |
|
AurelienUoU
|
fdc3c5e4a9
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-30 10:02:11 -06:00 |
|
AurelienUoU
|
5ac79f4805
|
Point to point documentation
|
2019-09-30 10:00:46 -06:00 |
tangxifan
|
b082e60c10
|
start refactoring instanciation of memory modules
|
2019-09-29 18:20:56 -06:00 |
|
tangxifan
|
3726e691f4
|
simplify the local wire generation for ccffs
|
2019-09-28 21:36:56 -06:00 |
|
tangxifan
|
1983e56557
|
make local configuration bus generation more general
|
2019-09-28 21:02:14 -06:00 |
Ganesh Gore
|
069f628bb0
|
Merge branch 'dev' of github.com:LNIS-Projects/OpenFPGA into ganesh_dev
|
2019-09-28 11:21:37 -06:00 |
|
tangxifan
|
433fc73460
|
refactored local encoder support for Verilog MUX generation
|
2019-09-27 23:10:43 -06:00 |
|
tangxifan
|
4da5035627
|
Connect CCFFs in a chain in a Verilog module
|
2019-09-27 20:50:12 -06:00 |
|
tangxifan
|
f0949fea2f
|
Merge branch 'dev' into refactoring
|
2019-09-27 18:09:58 -06:00 |
|
tangxifan
|
1e187f3d15
|
start adding memory circuit to Switch blocks
|
2019-09-27 18:08:37 -06:00 |
|
AurelienUoU
|
640922accd
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-27 16:54:13 -06:00 |
|
AurelienUoU
|
a93d7e57f7
|
Scan chain support in directlist
|
2019-09-27 16:53:00 -06:00 |
|
tangxifan
|
167778cf57
|
refactoring MUX Verilog instanciation in Switch block
|
2019-09-27 16:05:47 -06:00 |
|
Ganesh Gore
|
d269472daf
|
Updated formality python script
|
2019-09-27 14:00:57 -06:00 |
|
Ganesh Gore
|
438b592a8a
|
Appended VPR to genereate INI File
|
2019-09-27 14:00:27 -06:00 |
|
Ganesh Gore
|
a3e9b4aea9
|
Added mINI/lib - INI Read write to project
|
2019-09-27 13:58:48 -06:00 |
|
tangxifan
|
dbe1625267
|
Refactored Verilog wiring for formal verification ports in Switch Blocks
|
2019-09-27 13:51:22 -06:00 |
|
tangxifan
|
ead014e7d8
|
refactoring the configuration bus Verilog generation for MUXes
|
2019-09-27 11:47:34 -06:00 |
|
tangxifan
|
091bbd4d9c
|
start refactoring the num_config_bits for circuit model
|
2019-09-26 22:53:07 -06:00 |
|
tangxifan
|
8ccf681749
|
Merge branch 'dev' into refactoring
|
2019-09-26 21:00:19 -06:00 |
|
tangxifan
|
f0589cc2cf
|
refactoring mux Verilog generation for switch blocks
|
2019-09-26 20:59:19 -06:00 |
|
tangxifan
|
05eaa412b1
|
refactored short-connection of switch block
|
2019-09-26 14:31:05 -06:00 |
|
AurelienUoU
|
3b13c959f3
|
Finish renaming SCFF to CCFF
|
2019-09-26 14:04:40 -06:00 |
|
AurelienUoU
|
c4449b667f
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-26 11:34:59 -06:00 |
|
AurelienUoU
|
056219f180
|
Rename SCFF to CCFF, configuration chain flip flop
|
2019-09-26 11:32:57 -06:00 |
|
tangxifan
|
ea0da49e04
|
Merge branch 'dev' into refactoring
|
2019-09-25 21:06:06 -06:00 |
|
tangxifan
|
5bb40e7f74
|
refactored local wire generation for Switch block
|
2019-09-25 21:05:02 -06:00 |
|
AurelienUoU
|
e5faeb1400
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-25 16:50:53 -06:00 |
|
AurelienUoU
|
a35e2936b2
|
Fix verilog generation for direct connexion from directlist
|
2019-09-25 16:44:00 -06:00 |
|
tangxifan
|
2b0e2615fa
|
refactored sram port addition to module manager
|
2019-09-25 16:09:58 -06:00 |
|
tangxifan
|
c911f15a67
|
add formal verification port to SB Verilog generation
|
2019-09-23 21:15:45 -06:00 |
|
tangxifan
|
e1742b68ef
|
add pre-processing flag support for module manager
|
2019-09-23 20:25:53 -06:00 |
|
AurelienUoU
|
feddcbcb21
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-23 11:41:38 -06:00 |
|
tangxifan
|
d2ddbc19a3
|
refactoring the reserved sram port generation
|
2019-09-22 16:38:16 -06:00 |
|
tangxifan
|
8b3de892ef
|
simplify the regression test commands
|
2019-09-22 12:18:44 -06:00 |
|
tangxifan
|
2c4372c506
|
add reserved BLB/WL port naming
|
2019-09-22 12:16:43 -06:00 |
|
tangxifan
|
1e4177067d
|
remove port size in the module definition
|
2019-09-22 11:21:43 -06:00 |
|
tangxifan
|
5efea159c5
|
Simplify part of regression test to min_route_chan_width
|
2019-09-22 11:14:33 -06:00 |
|
Ganesh Gore
|
1dffe54807
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-09-22 00:21:25 -06:00 |
|
Ganesh Gore
|
50039a4b6e
|
Added remove run directory option
|
2019-09-21 23:35:56 -06:00 |
|
AurelienUoU
|
cc0bfdd548
|
Add testcase in regression test for architecture with 1 IO cell/IO block
|
2019-09-20 10:27:26 -06:00 |