tangxifan
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33e9b27cb8
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[Engine] Fixed a critical bug when building final bitstream, which may cause loss when merging BLs
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2021-09-25 20:22:27 -07:00 |
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tangxifan
|
29c351f5a4
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[Engine] Bug fix in estimating the configuration cycles for Verilog testbench generator
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2021-09-25 19:34:21 -07:00 |
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tangxifan
|
e06ac11630
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[Engine] Bug fix
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2021-09-25 19:21:16 -07:00 |
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tangxifan
|
3cf31f1565
|
[Engine] Fixed bugs
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2021-09-25 18:22:55 -07:00 |
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tangxifan
|
a56d1f4fdb
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[FPGA-Verilog] Upgraded testbench generator to support memory bank using flatten BL/WLs
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2021-09-25 17:49:15 -07:00 |
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tangxifan
|
386812777c
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[FPGA-Bitstream] Upgraded bitstream writer to support flatten BL/WLs
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2021-09-25 12:49:32 -07:00 |
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tangxifan
|
1a2a2a6e63
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[FPGA-Bitstream] Relax fabric bitstream address check
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2021-09-25 12:03:33 -07:00 |
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tangxifan
|
8b72447dad
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[FPA-Bistream] Updating fabric bitstream writer to organize bitstream for flatten BL/WLs
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2021-09-24 18:07:07 -07:00 |
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tangxifan
|
a49e3fe57a
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[FPGA-bitstream] Upgraded bitstream generator to support flatten BL/WLs for QL memory bank
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2021-09-24 16:30:18 -07:00 |
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tangxifan
|
025ee67bc7
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[Engine] Clear up compiler warning in tileable rr_graph builder
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2021-09-24 15:20:43 -07:00 |
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tangxifan
|
5f7617b682
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[Engine] Clear up compiler warnings in circuit library
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2021-09-24 15:18:50 -07:00 |
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tangxifan
|
f735c10b84
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[Engine] Clear up compiler warnings
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2021-09-24 15:18:31 -07:00 |
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tangxifan
|
2de4a460a8
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[Engine] Rework the function that counts the number of configurable children for fabric key writer and bitstream generator
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2021-09-24 15:15:32 -07:00 |
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tangxifan
|
74ffc8578f
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[Engine] Upgraded fabric generator to support flatten BL/WL bus for memory banks
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2021-09-24 15:05:25 -07:00 |
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tangxifan
|
be4c850d2d
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[Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs
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2021-09-24 12:03:35 -07:00 |
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tangxifan
|
18257b3fa1
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[Engine] Update BL/WL port addition for the top-level module in fabric generator
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2021-09-24 11:07:58 -07:00 |
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tangxifan
|
7e27c0caf3
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[Engine] Upgrading top-module fabric generation to support QL memory bank with flatten BL/WLs
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2021-09-23 16:16:39 -07:00 |
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tangxifan
|
8c281a22b0
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[Engine] Add check codes to validate circuit models for BL/WL protocols
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2021-09-23 14:39:16 -07:00 |
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tangxifan
|
6645b70ae3
|
[Engine] Upgrade parser to support BL/WL protocols
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2021-09-23 14:25:25 -07:00 |
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tangxifan
|
d4e3445153
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[Engine] update internal data structure for new syntax in configuration protocol
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2021-09-22 17:32:45 -07:00 |
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tangxifan
|
1ca1b0f3e9
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[Test] Deploy the new test case (flatten BL/WL for QL memory bank) to basic regression tests
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2021-09-22 15:58:05 -07:00 |
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tangxifan
|
655b195d8b
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[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
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2021-09-22 15:56:44 -07:00 |
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tangxifan
|
a98df811ed
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[Arch] Bug fix: wrong circuit model name was used for CCFF
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2021-09-22 15:50:47 -07:00 |
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tangxifan
|
53da5d49fe
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[Arch] Correct XML syntax errors
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2021-09-22 15:48:14 -07:00 |
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tangxifan
|
3cfd5c3531
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[Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks
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2021-09-22 15:04:59 -07:00 |
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tangxifan
|
212c5bd642
|
[Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization
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2021-09-22 15:04:19 -07:00 |
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tangxifan
|
b0aaab9c03
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[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
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2021-09-22 11:32:13 -07:00 |
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tangxifan
|
efed268585
|
[Test] Deploy new test (for multi-region QL memory bank) to basic regression tests
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2021-09-22 11:30:08 -07:00 |
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tangxifan
|
abfa380333
|
[Test] Added a test case to validate the fabric key of 2-region QL memory bank
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2021-09-22 11:27:09 -07:00 |
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tangxifan
|
337ed33b68
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[Test] Added a sample fabric key for 2-region QL memory bank
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2021-09-22 11:25:16 -07:00 |
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tangxifan
|
962acda810
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[Engine] Bug fix in fabric key generation when computing configurable children
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2021-09-22 11:09:46 -07:00 |
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tangxifan
|
ad432e4d95
|
[Engine] Bug fix in finding the start index of BL/WL for each column/row;
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2021-09-22 10:20:40 -07:00 |
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tangxifan
|
7db7e2d8f6
|
[Test] Deploy the new test case for multi region QL memory bank to basic regression tests
|
2021-09-22 10:05:27 -07:00 |
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tangxifan
|
d0fe12fadd
|
[Arch] Add an example OpenFPGA architecture for 2-region QL memory bank
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2021-09-22 10:03:39 -07:00 |
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tangxifan
|
51fc222d61
|
[Test] Added a new test case for multi-region QL memory bank
|
2021-09-22 10:01:33 -07:00 |
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tangxifan
|
10774dc15c
|
[Doc] Updated documentation about new syntax in fabric key
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2021-09-21 17:01:52 -07:00 |
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tangxifan
|
e09ab2298e
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[Engine] Bug fix in fabric key parser on identifying invalid coordinate
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2021-09-21 16:45:14 -07:00 |
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tangxifan
|
ab42239b94
|
[Test] Bug fix in the fabric key
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2021-09-21 16:44:58 -07:00 |
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tangxifan
|
f57aceff87
|
[Test] Deploy the load external key test case for ql memory bank to basic regression tests
|
2021-09-21 16:25:14 -07:00 |
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tangxifan
|
aad47ffbc6
|
[Test] Upgrade the sample fabric key to ql memory bank for a 2x2 fabric
|
2021-09-21 16:22:50 -07:00 |
|
tangxifan
|
1412121541
|
[Test] Added a new test to validate the fabric key parser for QL memory bank
|
2021-09-21 16:20:24 -07:00 |
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tangxifan
|
cd0d8b86fa
|
[Test] Add a random fabric key generated by OpenFPGA which is designed for QL memory bank
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2021-09-21 15:55:34 -07:00 |
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tangxifan
|
b0a471bdc9
|
[Engine] Bug fix in outputting fabric key with coordinates
|
2021-09-21 15:55:11 -07:00 |
|
tangxifan
|
7327850cf3
|
[Test] Deploy the fabric key test case for ql memory bank to basic regression tests
|
2021-09-21 15:43:54 -07:00 |
|
tangxifan
|
dc2d1d1c3c
|
[Test] Add a new test case to validate the correctness of fabric key file for ql memory bank
|
2021-09-21 15:42:20 -07:00 |
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tangxifan
|
7688c0570f
|
[Engine] Support coordinate definition in fabric key file format; Now QL memory bank can accept fabric key
|
2021-09-21 15:08:08 -07:00 |
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tangxifan
|
8a3ce62d70
|
Merge pull request #10 from RapidSilicon/phy_mem_bank
Support WLR signal in physical friendly memory bank
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2021-09-20 21:33:21 -07:00 |
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tangxifan
|
d9d959709c
|
[Doc] Add missing figures
|
2021-09-20 20:31:53 -07:00 |
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tangxifan
|
3146d2484f
|
[Doc] Update documentation on the WLR definition for circuit model
|
2021-09-20 17:21:33 -07:00 |
|
tangxifan
|
d36d1ebee2
|
[HDL] Temporarily disable WLR func in primitive HDL modeling
|
2021-09-20 17:07:51 -07:00 |