tangxifan
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3cbe266c44
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[Test] Bug fix on the test case for multi-mode FF and pin constraints
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2021-07-02 15:27:27 -06:00 |
Ganesh Gore
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c67807868c
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[bugFix] Benchamrk variable declaration
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2021-07-02 15:26:39 -06:00 |
tangxifan
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6e6c3e9fa4
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[Tool] Patch the critical bug in the use of signal polarity in pin constraints
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2021-07-02 15:26:21 -06:00 |
tangxifan
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3aacce2a96
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Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
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2021-07-02 14:04:42 -06:00 |
tangxifan
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a5101be2f6
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
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2021-07-02 13:58:33 -06:00 |
tangxifan
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2214575a0a
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Merge pull request #358 from lnis-uofu/ganesh_dev
Testcase for benchmark specific variables
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2021-07-02 13:54:07 -06:00 |
Ganesh Gore
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edd5be2cae
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[CI] Added testcase for benchmark variable
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2021-07-02 12:51:34 -06:00 |
tangxifan
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dcb89cb16b
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[Arch] Patch architecture due to missing mode bit definition
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2021-07-02 11:41:29 -06:00 |
tangxifan
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5286f9ba25
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[Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking
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2021-07-02 11:39:00 -06:00 |
ganeshgore
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b8bed59ecf
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Merge pull request #356 from lnis-uofu/pin_constraint_polarity
[WIP] Support custom default value in Pin Constraint File
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2021-07-02 10:20:20 -07:00 |
tangxifan
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02fd2a69b3
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[Script] Add dff with active-low async reset to default yosys tech lib
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2021-07-02 11:17:43 -06:00 |
tangxifan
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477e535344
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[HDL] Added a multi-mode FF design with configurable asynchronous reset
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2021-07-02 11:13:03 -06:00 |
tangxifan
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fd85f956c9
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[Arch] Update k4n4 arch with true multi-mode flip-flop
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2021-07-02 11:08:39 -06:00 |
tangxifan
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0b6a9b06f5
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[Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality
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2021-07-02 10:39:07 -06:00 |
tangxifan
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3906497ef5
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
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2021-07-02 10:27:40 -06:00 |
tangxifan
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f8fb056a42
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Merge branch 'master' into pin_constraint_polarity
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2021-07-02 10:05:17 -06:00 |
tangxifan
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e79da64e95
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Merge pull request #354 from lnis-uofu/ganesh_dev
[Flow] Allows benchmark specific Variable declaration
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2021-07-02 10:05:03 -06:00 |
tangxifan
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43afaca17c
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[Doc] Add more details about the new syntax
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2021-07-01 23:51:54 -06:00 |
tangxifan
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0851075bc9
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[Doc] Update documentation about the new feature in pin constraint file
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2021-07-01 23:47:36 -06:00 |
tangxifan
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9074bffa68
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[Tool] Support customized default value in pin constraint file
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2021-07-01 23:43:19 -06:00 |
Ganesh Gore
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1de1f2f2e2
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[FLOW] Variable in capital case
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2021-07-01 22:26:00 -06:00 |
Ganesh Gore
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81f9dff9ff
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[Flow] Allows benchmark specific var declaraton
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2021-07-01 22:19:53 -06:00 |
ganeshgore
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4818e08448
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Merge pull request #327 from lnis-uofu/verilog_testbench
added configuration benchmark files
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2021-07-01 20:38:16 -07:00 |
tangxifan
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b7356d23aa
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Merge branch 'master' into verilog_testbench
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2021-07-01 21:11:12 -06:00 |
tangxifan
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947f078a7e
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Merge pull request #353 from lnis-uofu/testbench_patch
Bug fix on the reset stimuli generator
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2021-07-01 21:10:40 -06:00 |
tangxifan
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d0e4f8521f
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[Tool] Bug fix on the reset stimuli
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2021-07-01 19:58:54 -06:00 |
ANDREW HARRIS POND
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1d281765ea
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fixed tab spacing
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2021-07-01 16:42:04 -06:00 |
ANDREW HARRIS POND
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808821bb8c
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fixed errors
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2021-07-01 16:40:03 -06:00 |
ANDREW HARRIS POND
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006b54c4bc
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ready for merge
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2021-07-01 15:35:39 -06:00 |
ANDREW HARRIS POND
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8513b8a4ff
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Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench
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2021-07-01 15:29:39 -06:00 |
ANDREW HARRIS POND
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2567fbee05
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ready to merge
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2021-07-01 15:28:59 -06:00 |
tangxifan
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04ceeefb0a
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Merge branch 'master' into verilog_testbench
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2021-07-01 14:43:26 -06:00 |
ANDREW HARRIS POND
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db9231c225
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tests failing with initial blocks
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2021-07-01 13:52:28 -06:00 |
komaljaved-rs
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be14e4f448
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added design_variables.yml
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2021-07-01 16:31:42 +05:00 |
komaljaved-rs
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01f79d89b8
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Merge branch 'master' of github.com:RapidSilicon/OpenFPGA_RS
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2021-07-01 16:24:12 +05:00 |
komaljaved-rs
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ff785569f0
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updated ci_test
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2021-07-01 16:23:55 +05:00 |
komaljaved-rs
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061811994d
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Update ci_test.yml
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2021-07-01 16:05:08 +05:00 |
komaljaved-rs
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6d11dc275d
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Update ci_test.yml
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2021-07-01 16:01:38 +05:00 |
komaljaved-rs
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4b8e178947
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Update ci_test.yml
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2021-07-01 15:44:59 +05:00 |
komaljaved-rs
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2469f25ef4
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updated submodule
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2021-07-01 15:14:59 +05:00 |
komaljaved-rs
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7a703659e7
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Merge branch 'master' of github.com:RapidSilicon/OpenFPGA_RS
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2021-07-01 15:08:26 +05:00 |
komaljaved-rs
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6559f71082
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added ci_scripts
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2021-07-01 15:07:37 +05:00 |
komaljaved-rs
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1e81dd897f
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Update ci_test.yml
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2021-07-01 14:47:59 +05:00 |
komaljaved-rs
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cbb4b32f7f
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Rename openfpga.yml to ci_test.yml
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2021-07-01 14:45:38 +05:00 |
komaljaved-rs
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4b6b0273ba
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Create openfpga.yml
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2021-07-01 14:44:48 +05:00 |
tangxifan
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a2cb153d54
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Merge pull request #349 from lnis-uofu/testbench_flag
More micro benchmarks on adder
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2021-06-30 16:39:21 -06:00 |
Andrew Pond
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fab2b069f0
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added signal gen regression test to shell script
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2021-06-30 16:18:09 -06:00 |
tangxifan
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602172bb27
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Merge branch 'testbench_flag' of https://github.com/LNIS-Projects/OpenFPGA into testbench_flag
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2021-06-30 15:29:53 -06:00 |
tangxifan
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a898537474
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[Benchmark] Remove redundant post-synthesis netlist for ``adder_8``
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2021-06-30 15:29:13 -06:00 |
tangxifan
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9786b52c73
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Merge branch 'master' into testbench_flag
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2021-06-30 15:18:53 -06:00 |