tangxifan
|
c8bf456097
|
bug fixing for memory leaking in allocating pb_rr_graph and power estimation
|
2019-06-15 12:23:36 -06:00 |
|
tangxifan
|
d3296d0975
|
developing tileable rr_graph builder
|
2019-06-14 22:35:42 -06:00 |
|
tangxifan
|
a33627606e
|
developing tileable routing track arrangement
|
2019-06-14 17:35:40 -06:00 |
AurelienUoU
|
29dadc51b4
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-06-14 11:46:02 -06:00 |
|
AurelienUoU
|
c76dbaac33
|
Update regression test avoiding overwritting files
|
2019-06-14 11:44:44 -06:00 |
|
tangxifan
|
4d2a3680be
|
support bus explicit port mapping to standard cells (for BRAMs)
|
2019-06-14 11:09:15 -06:00 |
|
tangxifan
|
0902d1e75a
|
c++ string is not working, use char which is stable
|
2019-06-13 18:38:46 -06:00 |
|
tangxifan
|
5f61cd8876
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
Conflicts:
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
|
2019-06-13 16:32:39 -06:00 |
|
tangxifan
|
af1628abfe
|
use bus port for primitives in Verilog generator
|
2019-06-13 16:26:58 -06:00 |
|
tangxifan
|
dddbbac85c
|
merge from multimode_clb bug fixing
|
2019-06-13 15:59:34 -06:00 |
|
tangxifan
|
e86874adca
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into fpga_spice
|
2019-06-13 15:54:27 -06:00 |
|
AurelienUoU
|
15b4cc9ecb
|
Error correction in memory generation for pb_types without modes
|
2019-06-13 15:34:25 -06:00 |
|
tangxifan
|
43128ad3f0
|
fix a bug in formal verification port for memory bank configuration circuits
|
2019-06-13 15:33:13 -06:00 |
|
tangxifan
|
44d21ebb90
|
fixed a bug in Verilog generator supporting SRAM5T
|
2019-06-13 14:42:39 -06:00 |
|
tangxifan
|
5ae4dec0af
|
fix bugs in CMakeList on enable/disable VPR Graphics
|
2019-06-12 22:48:00 -06:00 |
|
tangxifan
|
1d00e3665b
|
start developing tileable_rr_graph_builder
|
2019-06-11 16:50:40 -06:00 |
|
tangxifan
|
65b5454f3a
|
start developing tileable_rr_graph_builder
|
2019-06-11 16:49:10 -06:00 |
|
tangxifan
|
b359893852
|
Merge branch 'multimode_clb' into tileable_routing
|
2019-06-11 14:41:36 -06:00 |
|
AurelienUoU
|
bf13c1f731
|
Add a script to create a new file with correct path rather than overwrite the existing
|
2019-06-11 14:28:58 -06:00 |
Ganesh Gore
|
1da363f7f1
|
Merge remote-tracking branch 'lnis_open_fpga/fpga_spice' into ganesh_dev
|
2019-06-11 11:59:54 -06:00 |
|
tangxifan
|
7245917b9c
|
fix a bug for iopad SPICE generation
|
2019-06-11 11:43:56 -06:00 |
|
Ganesh Gore
|
1093e341a8
|
Added additional architecure files
|
2019-06-11 11:26:44 -06:00 |
|
tangxifan
|
1776ae3ec8
|
add explicit port mapping for inverters of memory decoders
|
2019-06-10 17:36:14 -06:00 |
|
tangxifan
|
8e3ad675e0
|
use sstream for rr_block verilog writer
|
2019-06-10 16:23:35 -06:00 |
|
tangxifan
|
009e5244d3
|
minor fix on the port direction of configuration peripherals for memory decoders
|
2019-06-10 15:39:35 -06:00 |
|
tangxifan
|
f43955037c
|
remove input port requirements for SRAM circuit module
|
2019-06-10 15:29:44 -06:00 |
|
tangxifan
|
e4f70771a2
|
updated SDC generator to embrace the RRGSB data structure
|
2019-06-10 14:47:27 -06:00 |
|
tangxifan
|
8a8f4153ce
|
use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
|
2019-06-10 12:50:10 -06:00 |
|
tangxifan
|
e31407f693
|
start cleaning up SDC generator with new RRGSB data structure
|
2019-06-10 10:57:26 -06:00 |
|
tangxifan
|
17bc7fc296
|
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
|
2019-06-08 20:11:22 -06:00 |
|
tangxifan
|
3a7139ee65
|
Merge branch 'tileable_sb' into multimode_clb
|
2019-06-08 15:15:52 -06:00 |
|
Xifan Tang
|
61e359efc5
|
Enable an option to disable/enable graphics in VPR compilation
|
2019-06-08 15:08:17 -06:00 |
|
tangxifan
|
90696def6d
|
remove vpr Makefile
|
2019-06-07 23:44:39 -06:00 |
|
tangxifan
|
d737c4ff46
|
fix path in regression test! TODO: must keep a duplicated copy for template.xml
|
2019-06-07 23:31:42 -06:00 |
|
tangxifan
|
3ad4a33751
|
update travis to use gcc8 and disable graphics for vpr when compile in osx
|
2019-06-07 22:38:21 -06:00 |
|
tangxifan
|
e8d52121c6
|
try j16 for travis in linux
|
2019-06-07 22:32:47 -06:00 |
|
tangxifan
|
1b02428c04
|
change travis gcc and gxx setting
|
2019-06-07 22:25:55 -06:00 |
|
tangxifan
|
f5b6ee6adf
|
update travis configuration and clean up repository
|
2019-06-07 22:19:11 -06:00 |
|
tangxifan
|
1f228dd42b
|
Merge branch 'tileable_sb' into multimode_clb
|
2019-06-07 20:23:32 -06:00 |
|
tangxifan
|
8c5ec4572d
|
revert string to sprintf
|
2019-06-07 20:20:41 -06:00 |
|
tangxifan
|
a55c577a61
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-06-07 18:56:32 -06:00 |
|
tangxifan
|
0f1ed19ad0
|
Revert to the use of sprintf instead std::string. Have no idea why string is not working
|
2019-06-07 18:54:57 -06:00 |
|
AurelienUoU
|
345a081eff
|
Correct error of target to rewrite file in regression test
|
2019-06-07 17:37:56 -06:00 |
|
tangxifan
|
44ce0e8834
|
update gsb unique module detection and fix formal verification port direction
|
2019-06-07 17:18:38 -06:00 |
|
tangxifan
|
24d53390d8
|
clean up DeviceRRGSB internal data and member functions
|
2019-06-07 14:45:56 -06:00 |
|
tangxifan
|
c9f810ceb6
|
update rr_gsb to build connection blocks
|
2019-06-07 11:01:55 -06:00 |
|
tangxifan
|
472aff5acb
|
add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
|
2019-06-06 23:45:21 -06:00 |
|
tangxifan
|
ce9fc5696c
|
rename rr_switch_block to rr_gsb, a generic block
|
2019-06-06 17:41:01 -06:00 |
|
tangxifan
|
8c1e7b799f
|
fixed critical bugs in Connection Block Unique Module detection
|
2019-06-06 16:31:50 -06:00 |
|
tangxifan
|
4f543c510c
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-06-06 12:50:03 -06:00 |