tangxifan
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824b56f14c
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fabric key can now accept instance name only; decoders are no longer part of the key
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2020-07-06 16:42:33 -06:00 |
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tangxifan
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83e26adf90
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add module usage types for future FPGA-SPICE development
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2020-07-04 22:33:54 -06:00 |
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tangxifan
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033c92c365
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precisely reserve memory for child blocks in bitstream manager
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2020-07-03 22:47:21 -06:00 |
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tangxifan
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57e6c84252
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add reserve net sources and sinks to module manager
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2020-06-29 22:49:11 -06:00 |
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tangxifan
|
66746f69da
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optimizing memory efficiency by reserving nets in module manager
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2020-06-29 21:27:43 -06:00 |
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tangxifan
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5368485bd6
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keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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0bee70bee6
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finish memory bank configuration protocol support.
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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0e16ee1030
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add configuration bus nets for memory bank decoders at top module
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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fa8dfc1fbd
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add configuration protocol ports to top module for memory bank organization
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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fbe05963e0
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add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol)
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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8298bbff78
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bug fixed in the fabric bitstream for frame-based configurable memories.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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bf9f62f0f7
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keep bug fixing for frame-based configuration protocol.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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65df309419
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bug fixing for frame-based configuration protocol and rename some naming function to be generic
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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c696e3d20f
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refine frame-based memory addition to compact the area
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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290dd1a8a6
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add frame decoder builder to all the module graph builder except the top-level
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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8864920460
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add frame-based memory module builder
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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3a26bb5eef
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add advanced check in configurable memories
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2020-06-11 19:31:09 -06:00 |
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tangxifan
|
e089b0ef22
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use constant string for inverted port naming
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2020-06-11 19:31:07 -06:00 |
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tangxifan
|
bf841b9a8e
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bug fixed in identifying wired LUT
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2020-04-22 17:28:16 -06:00 |
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tangxifan
|
e10cafe0a5
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Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
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2020-04-19 16:42:31 -06:00 |
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tangxifan
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e6c896d583
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now inout must be global port and I/O port so that it will appear in the top-level module
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2020-04-08 16:54:08 -06:00 |
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tangxifan
|
bcb86801fa
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bug fixed in gpio naming for module manager ports
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2020-04-05 17:26:44 -06:00 |
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tangxifan
|
5f4e7dc5d4
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support gpinput and gpoutput ports in module manager and circuit library
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2020-04-05 16:52:21 -06:00 |
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tangxifan
|
8b583b7917
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debugging spy port builder in module manager
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2020-04-05 16:01:25 -06:00 |
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tangxifan
|
836f722f20
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start supporting global output ports in module manager
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2020-04-05 15:19:46 -06:00 |
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tangxifan
|
7c9c2451f2
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debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
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2020-03-27 16:03:42 -06:00 |
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tangxifan
|
b6bdf78d95
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bug fixed for heterogeneous block instances in top module
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2020-03-24 17:39:26 -06:00 |
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tangxifan
|
fc6abc13fd
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add physical tile utils to identify pins that have Fc=0
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2020-03-21 21:02:47 -06:00 |
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tangxifan
|
b80e26e711
|
update bitstream generator to use sorted edges
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2020-03-08 15:36:47 -06:00 |
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tangxifan
|
4b7d2221d1
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adapt rr_graph builder utilized functions and move rr_graph utils from openfpga to vpr
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2020-03-04 13:55:53 -07:00 |
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tangxifan
|
ae899f3b11
|
bug fixed for clock names
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2020-02-27 16:51:55 -07:00 |
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tangxifan
|
bb671acac3
|
add formal random Verilog testbench generation
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2020-02-26 20:58:16 -07:00 |
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tangxifan
|
e9adb4fdbc
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add preconfig top module Verilog generation
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2020-02-26 20:38:01 -07:00 |
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tangxifan
|
759758421d
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found the bug in physical pb mode bits and fixed
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2020-02-25 23:45:49 -07:00 |
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tangxifan
|
075264e3e3
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debugging LUT bitstream generation
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2020-02-25 23:29:16 -07:00 |
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tangxifan
|
4024ed63cb
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add truth table build up for physical LUTs
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2020-02-25 22:39:42 -07:00 |
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tangxifan
|
ca038857d3
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add lut physical truth table to physical pb
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2020-02-25 13:34:13 -07:00 |
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tangxifan
|
2d86a02358
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refactored LUT bitstream generation to use vtr logic
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2020-02-25 12:45:13 -07:00 |
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tangxifan
|
921bf7dd7b
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use constant in device annotation
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2020-02-21 20:45:22 -07:00 |
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tangxifan
|
926e429374
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add save repacking results in physical pb
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2020-02-21 20:39:49 -07:00 |
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tangxifan
|
12f2888c7c
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add physical pb data structure and basic allocator
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2020-02-21 17:47:27 -07:00 |
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tangxifan
|
3e07d7d5e0
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finish net addition to LbRouter. Found a bug in pb pin fix-up. Need to consider clustered I/O block z offset
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2020-02-20 20:26:20 -07:00 |
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tangxifan
|
c855ab24f5
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put build top module memory connections online
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2020-02-14 11:07:04 -07:00 |
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tangxifan
|
9dc9c2c9f7
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add build top module connection functions
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2020-02-14 10:45:24 -07:00 |
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tangxifan
|
afe8278670
|
put routing module builder online
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2020-02-13 17:35:29 -07:00 |
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tangxifan
|
f11832b8cf
|
start integrating module graph builder
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2020-02-12 17:53:23 -07:00 |
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tangxifan
|
c78d3e9af1
|
add mux library builder
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2020-02-12 14:58:23 -07:00 |
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tangxifan
|
4367dba9b7
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move mux graph and decoder builders to vpr8 integration; ready to link the rr_switch to circuit models
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2020-02-11 21:02:58 -07:00 |
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tangxifan
|
175bef014a
|
add compact_routing hierarchy command
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2020-02-11 17:40:37 -07:00 |
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tangxifan
|
230c7b709a
|
put rr_gsb data structure online
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2020-02-09 00:20:44 -07:00 |
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tangxifan
|
3d7eff64b9
|
bug fixed for lut truth table fixup. Results look good
|
2020-02-06 17:47:25 -07:00 |
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tangxifan
|
ed9e038845
|
add functionality of LUT truth table fix-up
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2020-02-06 17:14:29 -07:00 |
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tangxifan
|
d2c47693f6
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add check codes for mode bits annotation to pb_types and clean up utils source files
|
2020-01-29 14:29:00 -07:00 |