tangxifan
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16b4e89326
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[Doc] Update documentation for VPR architectures
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2021-01-12 17:57:40 -07:00 |
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tangxifan
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7ccdff4543
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[Arch] Add an architecture using 4 clocks
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2021-01-12 17:55:57 -07:00 |
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tangxifan
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aaf582acc5
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[Arch] Bug fix
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2021-01-10 11:05:57 -07:00 |
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tangxifan
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f21d22f691
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[Doc] Update README for new architectures
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2021-01-10 10:54:59 -07:00 |
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tangxifan
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853e7b1a40
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[Arch] Add vpr architecture where I/O can be either combinational or registered
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2021-01-10 10:54:09 -07:00 |
Lalit Sharma
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891e2f8aa3
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Adding arch xml from SOFA repo. Also updating the script with its file location
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2020-12-16 04:14:18 -08:00 |
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tangxifan
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6001da3a40
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[Arch] Bug fix in tileable I/O arch example
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2020-12-04 17:56:54 -07:00 |
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tangxifan
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1d0bdcfeca
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[Arch] Simplify the grid layout modeling
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2020-12-04 17:38:44 -07:00 |
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tangxifan
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1c3f625e41
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[Arch] Force empty tiles at corners for tileable I/O arch example
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2020-12-04 17:11:06 -07:00 |
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tangxifan
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186eb0f0a4
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[Arch] Add tileable I/O architecture example
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2020-12-04 15:59:39 -07:00 |
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tangxifan
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7a0a3398d4
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[Arch] Add new architecture to test global reset ports defined thru tile ports
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2020-11-30 17:43:41 -07:00 |
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tangxifan
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a60bd4d14a
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[Arch] Bug fix in nature fracturable architecture
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2020-11-25 22:48:26 -07:00 |
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tangxifan
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eda671592e
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[Doc] Update README about new keyword about fracturable LUT
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2020-11-25 22:12:56 -07:00 |
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tangxifan
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0f841aa6d1
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[Arch] Add an example architecture using native fracturable LUT
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2020-11-25 22:11:14 -07:00 |
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tangxifan
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a6531d9e8d
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[Arch] Add k4 arch using global clock from tile port (with zero fc)
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2020-11-10 19:17:34 -07:00 |
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tangxifan
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bce8233019
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[Arch] Bug fix in caravel arch
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2020-11-04 20:58:58 -07:00 |
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tangxifan
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aebf7453d0
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[Arch] Add architecture files with compatible I/O capacity with caravel SoC
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2020-11-04 16:57:00 -07:00 |
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tangxifan
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cf455df555
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[Arch] Add architecture for bottom-right and top-left tile organization
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2020-11-04 16:24:36 -07:00 |
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tangxifan
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46ca406f10
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[Arch] Add a new vpr architecture with new tile organization
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2020-11-04 16:20:01 -07:00 |
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tangxifan
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049ca14461
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[Doc] Add new naming rules for vpr architecture files
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2020-11-04 16:17:56 -07:00 |
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tangxifan
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3b49e6d090
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[Arch] Patch embedded IO architecture by forcing only 1 pad per block
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2020-11-02 15:39:31 -07:00 |
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tangxifan
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a7e7fa2005
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[Arch] Update arch with true embedded I/O definition
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2020-11-02 13:29:40 -07:00 |
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tangxifan
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8c8190047f
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[Arch] Rename architecture files for embedded I/Os
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2020-11-02 13:15:19 -07:00 |
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tangxifan
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795b30f76b
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[Arch] Add VPR architecture with partial pin equivalence
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2020-11-02 11:54:25 -07:00 |
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tangxifan
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951a47b19c
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[Architecture] Add k4 series architecture using pattern-based local routing
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2020-09-23 16:05:39 -06:00 |
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tangxifan
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70b8b02f74
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[Architecture] Add vpr architecture for k4n4 with fracturable 32-bit multiplier
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2020-09-22 15:32:11 -06:00 |
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tangxifan
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8a3934b749
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[Architecture Add vpr architecture for k4n4 using multiple wire segments
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2020-09-22 12:35:39 -06:00 |
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tangxifan
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daf776b7b1
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[Architecture] Add k4n4 architecture with bram block for basic tests
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2020-09-22 12:22:32 -06:00 |
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tangxifan
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7a6f5a06f7
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[Architecture] Add a k4n4 architecture with carry chain to quick test
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2020-09-22 11:33:56 -06:00 |
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tangxifan
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aa5f5fc7e0
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[Architecture] Bring back pin equivalence for no local routing architecture
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2020-09-21 22:22:39 -06:00 |
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tangxifan
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a8a269aa82
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[Architecture] Temporary patch for the no local routing architecture
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2020-09-21 19:51:23 -06:00 |
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tangxifan
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7a57cc9cf4
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[Architecture] A new device layout to k4n4 to test untileable architecture
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2020-09-21 18:36:50 -06:00 |
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tangxifan
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2bbfcb5753
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[Architecture] Add a new device layout to k4n4 for testing tileable routing
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2020-09-21 18:34:31 -06:00 |
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tangxifan
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e1c5947143
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[Architecture] Add auto layout and fixed layout to architectures
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2020-09-21 18:01:51 -06:00 |
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tangxifan
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d7f8b3abad
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[Architecture] Add k4 N4 untilable architecture
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2020-09-21 17:44:37 -06:00 |
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tangxifan
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e9c0e90544
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[Architecture] Add a VPR architectue using fracturable LUT4
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2020-09-21 17:37:26 -06:00 |
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tangxifan
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ca1bafc688
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[OpenFPGA Architecture] Add full pin equivalence to full output crossbar architecture
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2020-09-16 19:26:12 -06:00 |
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tangxifan
|
c22d8e2421
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[Architecture] Bug fix in no local routing architecture
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2020-09-16 18:07:52 -06:00 |
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tangxifan
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f5b7ac6269
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[OpenFPGA Architecture] Add a new architecture with no local routing
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2020-09-16 18:04:55 -06:00 |
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tangxifan
|
030d7f02f8
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[OpenFPGA architecture] bug fix in the fully connected output crossbar architecture
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2020-09-16 17:30:08 -06:00 |
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tangxifan
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3c0faf0021
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[OpenFPGA Architecture] Add a new architecture with fully connected crossbar at CLB outputs
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2020-09-16 17:27:24 -06:00 |
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tangxifan
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6c925dcded
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[regression test] Add more tests for thru channels and deploy to CI
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2020-08-19 20:11:37 -06:00 |
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tangxifan
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881672d46a
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update thru channel arch for avoid buggy pin locations
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2020-08-19 19:52:35 -06:00 |
|
tangxifan
|
3273f441fe
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bug fix in the flagship vpr arch
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2020-08-19 15:23:20 -06:00 |
|
tangxifan
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d7efdf35b6
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add custom pin location to the flagship vpr arch with frac mem and dsp
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2020-08-19 11:15:25 -06:00 |
|
tangxifan
|
3ee4e10aa8
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bug fix in the frac mem & DSP vpr arch
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2020-08-18 17:25:45 -06:00 |
|
tangxifan
|
f833e0ec66
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add a flagship architecture using fracturable memory and dsp
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2020-08-17 17:49:51 -06:00 |
|
tangxifan
|
1ca2829868
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update readme for vpr architecture naming
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2020-08-17 13:54:26 -06:00 |
|
tangxifan
|
534c609e17
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add fixed layouts to a flagship architecture to test bitstream generation runtime
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2020-07-28 11:51:50 -06:00 |
|
tangxifan
|
f754c8af06
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use k6_n10 architecture to reduce CI runtime
|
2020-07-22 13:45:55 -06:00 |
|
tangxifan
|
1e6955aaa4
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rename arch directory to be clear for its usage
|
2020-07-04 19:13:28 -06:00 |