Commit Graph

1547 Commits

Author SHA1 Message Date
tangxifan 1e4177067d remove port size in the module definition 2019-09-22 11:21:43 -06:00
tangxifan 5efea159c5 Simplify part of regression test to min_route_chan_width 2019-09-22 11:14:33 -06:00
Ganesh Gore 1dffe54807 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-22 00:21:25 -06:00
Ganesh Gore 50039a4b6e Added remove run directory option 2019-09-21 23:35:56 -06:00
AurelienUoU cc0bfdd548 Add testcase in regression test for architecture with 1 IO cell/IO block 2019-09-20 10:27:26 -06:00
tangxifan 0ff0c8cf06 bug fix for IO=1 2019-09-19 15:43:25 -06:00
tangxifan 4e7af5cdc5 update tileable_routing test 2019-09-18 15:59:32 -06:00
tangxifan e0b253d30a minor fix for non-LUT intermedate buffer case 2019-09-18 15:15:03 -06:00
tangxifan 0f0d06aad7 add non-LUT intermediate buffer to test and apply minor bug fix 2019-09-18 15:04:51 -06:00
Ganesh Gore 8afcba2c45 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-18 12:15:42 -06:00
Ganesh Gore cd5fd6ce6c Added explicit checking to VVP execution 2019-09-18 12:14:26 -06:00
Ganesh Gore 56c40ca06d Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-17 22:12:11 -06:00
Ganesh Gore 169732ccc1 Added verbose option in VVP output 2019-09-17 22:09:37 -06:00
tangxifan d7ac7d3649 start refactoring the switch block verilog generation 2019-09-17 20:40:26 -06:00
Ganesh Gore 7be83235a0 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-16 21:25:26 -06:00
Ganesh Gore 678e3181ba Made compact_routing_hierarchy options uncond 2019-09-16 21:22:13 -06:00
tangxifan 5abbfd6a0f add tileable routing to regression test 2019-09-16 20:45:02 -06:00
tangxifan 2294aecef2 remove old codes and compact new codes 2019-09-16 20:19:14 -06:00
tangxifan c5ee81541a remove dead codes in routing module generation 2019-09-16 18:47:01 -06:00
tangxifan 0963852091 remove useless global ports for routing channel modules
Need to rework the top-netlist generator before the new module generator can be plugged-in
2019-09-16 18:38:37 -06:00
tangxifan d83cad7c2e refactoring Verilog generation for routing channels 2019-09-16 17:35:51 -06:00
Baudouin Chauviere d5ebe66ad9 Bug fix 2019-09-16 10:57:52 -06:00
Ganesh Gore 81b9c5b266 Added flag for VVP exit code 2019-09-14 12:35:47 -06:00
Ganesh Gore d90329678a Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2019-09-14 12:11:36 -06:00
Ganesh Gore ec3854a648 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-14 00:14:17 -06:00
Ganesh Gore e5c99c8b12 Quick terminate on fail added 2019-09-13 23:56:38 -06:00
Ganesh Gore 10eba0f78c Updated script.sh with new paramters 2019-09-13 23:31:23 -06:00
Ganesh Gore bd9e57bc37 Added better task name 2019-09-13 23:30:42 -06:00
Ganesh Gore a6e592247e Replaced options exit_on fail and show_thread logs 2019-09-13 22:50:20 -06:00
tangxifan f69ce708ca rework on the order of top-level functions 2019-09-13 21:59:52 -06:00
tangxifan 29e80d157c Start developing BitstreamContext 2019-09-13 21:27:47 -06:00
tangxifan e64cfc5852 start refactoring memory decoders 2019-09-13 20:58:55 -06:00
Baudouin Chauviere 1801820429 Merge branch 'explicit_verilog' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog 2019-09-13 16:03:13 -06:00
Baudouin Chauviere 737cfb1086 Correction to the explicit Verilog for FPGAs above 2x2 2019-09-13 16:02:06 -06:00
Baudouin Chauviere 63e6ed21b5 Fully functional 2019-09-13 16:02:06 -06:00
egiacomin f9f3e290c0 Update building.md 2019-09-13 15:59:51 -06:00
tangxifan d6fc9c1c71 Find out the mem circuit is so correlated to the new MUX Verilog. Plug-in later 2019-09-13 15:36:35 -06:00
tangxifan 009c0d63b5 refactored the memory bank. Ready to plug-in the test 2019-09-13 15:05:31 -06:00
tangxifan 99c30fa7dd keep refactoring the memory Verilog generation 2019-09-13 14:02:04 -06:00
tangxifan 56f40cf46c light modification on Verilog Mux generation and start refactoring memory Verilog generation 2019-09-13 12:22:57 -06:00
tangxifan d8b9349066 remove legacy codes 2019-09-13 11:48:25 -06:00
tangxifan b920f0fc38 refactored user template Verilog generation 2019-09-13 11:41:54 -06:00
tangxifan 0e6c88dd52 delete legacy codes for wire Verilog generation 2019-09-12 21:06:53 -06:00
tangxifan c20e182484 plugged in the refactored wire Verilog generation 2019-09-12 20:56:30 -06:00
tangxifan 2b829238b5 refactored wire Verilog generation 2019-09-12 20:49:02 -06:00
tangxifan 79fa858f36 remove unused ports for Verilog modules 2019-09-11 19:39:59 -06:00
tangxifan 2bed51bf29 minor bug fix for echo 2019-09-11 17:41:45 -06:00
tangxifan 0399319212 refactored LUT Verilog generation 2019-09-11 17:04:43 -06:00
tangxifan 6a5b50facf refactored RRAM MUX verilog generation 2019-09-10 20:45:44 -06:00
tangxifan 0711aa1bd6 minor bug fixing 2019-09-10 16:56:14 -06:00