0a0d10b36d
[HDL] Bug fix in Verilog syntax
2021-06-22 16:18:46 -06:00
07dcf3ad27
[HDL] Add more micro benchmarks for counter, and-gate and mac unit
2021-06-21 16:48:35 -06:00
16fff90607
[Benchmark] Add microbenchmark 1-bit blinking
2021-05-06 15:17:27 -06:00
a571b063b6
[Benchmark] Add 1k DPRAM benchmark which can fit new arch
2021-04-28 11:26:31 -06:00
7d059f7407
[Benchmark] Bug fix in dual port ram 16k benchmark
2021-04-27 23:33:20 -06:00
3c1c33bf1e
[Benchmark] Add a microbenchmark just fit 16k dual port ram
2021-04-27 22:51:43 -06:00
7e2368158e
[Benchmark] move benchmarks to microbenchmark category
2021-04-27 22:12:30 -06:00
5a85ec9fa0
[Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised
2021-04-27 22:09:10 -06:00
1d498bb296
[Benchmark] Add a scalable micro benchmark fifo
2021-04-27 15:26:52 -06:00
200b6d39a6
[Benchmark] Add more micro benchmarks for mac ranging from 8 bit to 32 bit
2021-04-23 20:36:28 -06:00
671394ec2c
[Benchmark] Add microbenchmarks for mac with different sizes for DSP testing
2021-04-23 20:33:43 -06:00
b203ef7bc2
[Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs
2021-04-21 14:03:51 -06:00
c020333512
Merge branch 'master' into dff_techmap
2021-04-16 20:54:28 -06:00
bbdc0e53af
[Benchmark] Add 8-bit counter benchmark using asynchronous reset to test fracff architectures
2021-04-16 20:14:48 -06:00
e46c6e75a3
[Benchmark] Add missing RTL for IWLS2005 benchmarks
2021-04-16 16:50:41 -06:00
26d3b5a954
[Benchmark] Reorganize iwls2005 benchmark: separate the location of rtl and testbenches
2021-04-16 16:08:58 -06:00
86ad572530
[Benchmark] Add opencore RTLs from IWLS 2005 benchmarks
2021-04-16 14:27:54 -06:00
44d97ead86
Merge branch 'master' into hetergeneous_arch
2021-03-23 17:05:03 -06:00
be03eafd66
[Benchmark] Add a micro benchmark: 8-bit multiply and accumulate
2021-03-23 15:33:37 -06:00
55d1004cf2
[Benchmark] Add missing DPRAM module to LU32PEEng
2021-03-22 14:41:38 -06:00
5fc83ebea3
[Benchmark] Add missing DPRAM modules to LU8PEEng
2021-03-22 14:38:00 -06:00
b828f91a78
[Benchmark] Add missing DPRAM and SPRAM modules to mcml
2021-03-22 14:13:05 -06:00
b906ab814e
[Benchmark] Add missing DPRAM module to mkPktMerge
2021-03-22 12:51:23 -06:00
310c2a9495
[Benchmark] Add missing DPRAM module to mkDelayWorker32B
2021-03-22 12:51:02 -06:00
707247283c
[Benchmark] Add missing DPRAM module to mkSMAdapter4B
2021-03-22 12:50:39 -06:00
eb056e2afd
[Benchmark] Add missing DPRAM module to or1200
2021-03-22 12:50:17 -06:00
169ee53b79
[Benchmark] Add missing modules to VTR benchmarks
2021-03-20 22:53:17 -06:00
2bd8ef2af9
[Benchmark] Patch boundtop.v with missing SPRAM module
2021-03-20 21:00:53 -06:00
6bf4880c50
[benchmark] Add vtr benchmark
2021-03-17 15:24:26 -06:00
ce76c58422
add shift register test case
2021-03-05 09:06:05 -08:00
2dbdc2644f
[Benchmark] Remove replicate micro benchmarks
2021-02-22 10:22:19 -07:00
be5e0cdea9
Merge pull request #241 from lnis-uofu/add_quicklogic_tests
...
Adding quicklogic tests and updating the corresponding conf file to r…
2021-02-22 09:50:26 +05:30
576e6753f6
Removing 2 more tests which are variant of and design
2021-02-19 09:11:19 -08:00
d4c5a5655a
Removing blif file as well as and2 testcase
2021-02-19 08:55:17 -08:00
1f097abe99
[Benchmark] Add micro benchmark for FIR filter
2021-02-18 19:37:44 -07:00
44a979288b
Adding quicklogic tests and updating the corresponding conf file to run them
2021-02-16 23:08:38 -08:00
1712ee4edb
[Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture
2021-02-09 15:41:21 -07:00
8853370c60
[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
2021-02-04 20:20:10 -07:00
4c825b27b3
[Benchmark] Change to use adder lut4 to be consistent with architecture
2021-02-03 09:37:48 -07:00
05d63567d0
[Benchmark] Use latest adder eblif file
2021-02-03 09:21:38 -07:00
2c06960e4f
[Benchmark] Add subckt definition to micro benchmark and2.eblif
2021-02-02 15:51:16 -07:00
dc320182b0
[Benchmark] Bug fix in the and2 eblif to cooperate with the architecture models
2021-02-02 15:04:43 -07:00
62803dc044
[Benchmark] Add eblif example for and2 benchmark
2021-02-02 14:59:31 -07:00
39e6f62d91
[Benchmark] Use eblif in naming the adder_8 micro benchmark
2021-02-02 09:32:42 -07:00
7f0f7a1c70
[Benchmark] Add micro benchmark 8-bit adder synthesized by Quicklogic script
2021-02-01 12:05:04 -07:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
...
* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
9a906e787b
[Benchmark] Add post-yosys .v file for counter 4-bit with dual clock
2021-01-13 15:43:31 -07:00
7af6d7f07d
[Benchmark] change the pin sequence of counter4bit_2clock to be easy for testbench generation
2021-01-13 15:38:44 -07:00
91f12071d5
[Test] Use counter4bit in the multi-clock test
2021-01-13 13:34:59 -07:00
ccf3e037ff
[Benchmark] Change multi-clock counter from 8-bit to 4-bit
2021-01-13 13:31:06 -07:00
tangxifan
Tarachand Pagarani
Lalit Narain Sharma
Lalit Sharma
AurelienAlacchi