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104 Commits

Author SHA1 Message Date
tangxifan 9832722056 [test] now add QuickLogic memory bank to fpga bitstream regression tests 2022-05-25 11:42:32 +08:00
tangxifan 9f56e61342 [arch] syntax 2022-05-09 17:13:57 +08:00
tangxifan 812af4f722 [arch] add arch that supports negative edge triggered flip-flop 2022-05-09 16:32:01 +08:00
tangxifan f8ef3df560 [Test] Now use 4x4 fabric in testing write_rr_gsb commands 2022-01-26 11:41:48 -08:00
tangxifan 27caeb1d1f [Arch] Patched VPR arch 2022-01-02 20:47:22 -08:00
tangxifan 384a1e58d6 [Arch] Patch architecture using DSP with registers 2022-01-02 20:44:43 -08:00
tangxifan e3baec63f8 [Arch] Bug fix on architecture with registerable DSP 2022-01-02 20:35:48 -08:00
tangxifan f667065f75 [Arch] Bug fix in DSP with registers architecture 2022-01-02 20:34:26 -08:00
tangxifan 9c476ed5db [Arch] Syntax error fix 2022-01-02 20:27:00 -08:00
tangxifan 7598455497 [Doc] Update naming convention for architecture files 2022-01-02 19:51:09 -08:00
tangxifan 48491fcf52 [Flow] Add example architecture for DSP with input and output registers 2022-01-02 19:47:39 -08:00
tangxifan 81966c2131 [Doc] Update README for DSP blocks 2022-01-02 18:27:37 -08:00
tangxifan be47e78289 [Arch] Change arch for Sapone test 2021-10-30 15:23:19 -07:00
tangxifan dcb89cb16b [Arch] Patch architecture due to missing mode bit definition 2021-07-02 11:41:29 -06:00
tangxifan fd85f956c9 [Arch] Update k4n4 arch with true multi-mode flip-flop 2021-07-02 11:08:39 -06:00
tangxifan bc34efe337 [Arch] Bug fix in the architecture using BRAM spanning two columns 2021-04-28 14:32:17 -06:00
tangxifan be98775ae5 [Arch] Reduce the size of DPRAM in example architecture to accelerate testing 2021-04-28 10:45:10 -06:00
tangxifan 79b27a6329 [Arch] Patch arch using DPRAM block with wide = 2 2021-04-28 10:29:09 -06:00
tangxifan 834657f2da [Arch] Patch arch using 16kbit DPRAM due to wrong addr sizes 2021-04-27 23:41:14 -06:00
tangxifan 0f8aaae2bc [Arch] Patch architecture using 16kbit dual port RAM 2021-04-27 19:54:34 -06:00
tangxifan 8c007c7c49 [Arch] Add a new example architecture where a DSP block occupies a 2x2 grid 2021-04-26 16:28:10 -06:00
tangxifan 7d4c5e3cd1 [Arch] Patch pin location of dsp8 to be evenly placed on the right side of a height=2 block 2021-04-26 12:00:57 -06:00
tangxifan 6e87b8875b [Arch] Patch the pin location of frac dsp16 to appear on the top side of a height=2 block 2021-04-26 11:59:25 -06:00
tangxifan 5adffad602 [Arch] Changes to the arch to avoid a bug where the rr_nodes at top side of a heterogenenous block have no fan-in!!! 2021-04-24 15:49:53 -06:00
tangxifan 4f454abfde [Arch] Add a new architecture using fracturable 16-bit DSP blocks 2021-04-24 14:01:42 -06:00
tangxifan ce6018e123 [Arch] Enriched DFF model to support active-low/high FFs 2021-04-21 22:48:31 -06:00
tangxifan 9d9840d9b7 [Arch] Add architecture using multi-mode DFFs 2021-04-21 19:49:48 -06:00
tangxifan e3dafe99da [Arch] Revert to old version arch due to editing by mistake 2021-04-16 20:58:32 -06:00
tangxifan 16e02ef485 [Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script 2021-04-16 20:47:39 -06:00
tangxifan 4239bb4e68 [Arch] Patch architecture files using multi-mode DFFs 2021-04-16 19:59:55 -06:00
tangxifan f2f7f010ea [Arch] Add new architectures using DFF with reset in VPR 2021-04-16 19:26:18 -06:00
tangxifan 64294ae4eb [Doc] Update README for architecture files due to new architecture features 2021-04-16 19:25:54 -06:00
tangxifan 44d97ead86
Merge branch 'master' into hetergeneous_arch 2021-03-23 17:05:03 -06:00
tangxifan fdec72b5bc [Arch] Add an example architecture with 8-bit single-mode multiplier 2021-03-23 15:35:06 -06:00
tangxifan 911979a731 [Arch] Update heterogenous architecture for vtr benchmark by adding mult36 2021-03-20 18:04:59 -06:00
tangxifan 910f8471dd [Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys) 2021-03-17 15:10:05 -06:00
tangxifan ad25944e59 [Arch] Patched superLUT architecture example when trying adder8 synthesis script 2021-02-23 19:00:27 -07:00
tangxifan ca135f3325 [Arch] Add flagship architecture with 8-clock 2021-02-22 15:01:18 -07:00
tangxifan 1c09c55e9f [Arch] Add hetergenenous 8-clock FPGA architecture 2021-02-22 13:38:50 -07:00
tangxifan 0ac75723af [Arch] Add new architecture with 8 clocks 2021-02-22 11:00:45 -07:00
tangxifan b9c2564a7e [Arch] Add VPR architecture with 5 clocks to test counter with 5 clocks 2021-02-22 10:49:21 -07:00
tangxifan 7dcc14d73f [Arch] Bug fix in the example arch with super LUT 2021-02-09 15:52:22 -07:00
tangxifan 304b26c97f [Arch] Add example architectures for superLUT circuit model 2021-02-09 15:11:12 -07:00
AurelienAlacchi 00fc3d7622
Merge pull request #217 from lnis-uofu/dev 
Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
 2021-02-05 09:53:28 -07:00
tangxifan dc09c47411 [Arch] Remove packable from architecture files and replace with disable_packing 2021-02-04 18:03:56 -07:00
tangxifan 66bc370c4d [Arch] Use disable_packing in architecture library 2021-02-04 16:29:03 -07:00
tangxifan a4c266d59a [Arch] Add pack patterns for soft adders; Still fail in packing 2021-02-03 19:11:15 -07:00
tangxifan cac1160bf7 [Arch] Patch QLSOFA architecture to support carry chain pattern; Still buggy for VPR packer; Looking for a solution 2021-02-03 11:20:56 -07:00
tangxifan 021520783b [Arch] Add dummy timing info to adder_lut4 and carry_follower model 2021-02-02 15:49:43 -07:00
tangxifan 10302752a7 [Arch] Bug fix in architecture. Now soft adder modes are accepted 2021-02-01 13:43:39 -07:00