tangxifan
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1864b080a2
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[Architecture] Bug fix in configurable latch Verilog HDL
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2020-09-23 18:28:45 -06:00 |
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tangxifan
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906191e931
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[Architecture] Use strict latch Verilog HDL in frame-based procotol
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2020-09-23 17:58:13 -06:00 |
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tangxifan
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645db17168
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[Architecture] Patch DFF Verilog HDL
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2020-09-23 17:52:59 -06:00 |
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tangxifan
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092ada39f4
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[Architecture] Add Verilog HDL for DFF with write enable
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2020-09-23 17:49:30 -06:00 |
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tangxifan
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a94c2655c2
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[Architecture] Patch Verilog HDL for configurable latch
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2020-09-23 17:21:30 -06:00 |
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tangxifan
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b242ab79bd
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[OpenFPGA Flow] Add Verilog HDL for configurable latch with active-low reset
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2020-09-23 17:19:02 -06:00 |
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tangxifan
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61bcbaafd8
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[Architecture] Add Verilog HDL for fracturable 32-bit multiplier
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2020-09-22 15:15:19 -06:00 |
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tangxifan
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ddf999b6b9
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[Architecture] Add verilog HDL for dual-port BRAM 1k
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2020-09-22 12:23:28 -06:00 |
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tangxifan
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743167521a
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add Verilog design for fracturable 32k memory
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2020-08-18 21:13:46 -06:00 |
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tangxifan
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21c7eaa9cf
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add 36-bit fracturable multiplier Verilog
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2020-08-18 14:06:08 -06:00 |
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tangxifan
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baa2c6b7ef
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update arch to support reset signal for SRAm
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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82b04ae3f0
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add SRAM verilog for memory bank usage
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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b5e5182f52
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frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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583c15131b
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change configuration latch to be triggered at negative edge; Frame-based fabric passed Modelsim verification but failed in iVerilog
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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f5968fda52
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add configurable latch Verilog codes
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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214d98fbcd
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add register chain and scan chain to Travis CI
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2020-04-12 15:28:22 -06:00 |
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tangxifan
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da5af8f0e0
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try to add aib test case. bug found
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2020-04-12 14:54:45 -06:00 |
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tangxifan
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600a48edc7
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add test case of BRAM to Travis CI
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2020-04-12 14:27:05 -06:00 |
AurelienUoU
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09fd2afa9c
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Adding heterogeneous synthesis requirements
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2019-12-03 16:09:26 -07:00 |
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AurelienUoU
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2f14716f13
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Adding DPRAM behavioural Verilog netlist and its TB
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2019-12-03 13:58:20 -07:00 |
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tangxifan
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d391983e8c
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passing regression test on dpram benchmarks
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2019-11-07 14:57:46 -07:00 |
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tangxifan
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56b4ee008e
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add test for heterogeneous FPGA and fix bugs
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2019-11-06 17:45:11 -07:00 |
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tangxifan
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4ea5756be6
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bug fixed for std cell MUX2 architecture and add the case to regression tests
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2019-11-06 16:06:47 -07:00 |
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tangxifan
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09eb373a6e
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bug fixing for autocheck top testbench where clock port is not default names
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2019-11-06 12:21:20 -07:00 |
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tangxifan
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a308a13d7c
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use prefix instead of lib_name when building modules, then use lib_name for standard cell modules
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2019-11-05 15:41:59 -07:00 |
Ganesh Gore
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370a5ed408
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Bug Fix: shifter ff.v include path to tcl script
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2019-11-01 18:22:40 -06:00 |
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tangxifan
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4398cffaaa
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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Ganesh Gore
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7bfc48b8e4
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Moved spice and verilog netlist folder location
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2019-08-17 01:49:49 -06:00 |