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OpenFPGA
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4,484 Commits 71 Branches 8 Tags 105 MiB
Commit Graph

247 Commits

Author SHA1 Message Date
tangxifan 33064ca4cf [FPGA-SDC] Add a new option ``--no_time_stamp`` to all the commands 2022-01-25 15:51:28 -08:00
tangxifan b09e13b42c [FPGA-Verilog] Fixed a bug on invalid option of a command 2022-01-25 13:45:44 -08:00
tangxifan 25143d07f1 [FPGA-Bitstream] Now has a new option ``--no_time_stamp`` to all the commands that output bitstream files 2022-01-25 13:37:54 -08:00
tangxifan 62b57b05d2 [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
tangxifan 6586ea7816 [Engine] Bug fix for fabric key writer which errors out when there is no BL/WL banks in the architecture 2021-10-11 09:40:02 -07:00
tangxifan b9c540ec3f [Engine] Upgrade fabric key writer to support BL/WL shift register banks 2021-10-10 21:14:14 -07:00
tangxifan 34575f7222 [FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank 2021-10-09 20:39:45 -07:00
tangxifan 8f5f30792f [Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface 2021-10-08 15:25:37 -07:00
tangxifan 2ea9826b17 [FPGA-Bitstream] Bug fix in wrong option name 2021-10-05 18:58:47 -07:00
tangxifan ad54c8547e [FPGA-Bitstream] Added an option to ``write_fabric_bitstream`` command to enable outputting don't care bits in bitstream files 2021-10-05 18:54:02 -07:00
tangxifan 977d81679d [Engine] Upgrade check codes for WL CCFF 2021-10-01 17:23:10 -07:00
tangxifan 2d4c200d58 [FPGA-Verilog] Now FPGA-Verilog can output shift register bank netlists 2021-09-29 20:56:02 -07:00
tangxifan b87b7a99c5 [Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators 2021-09-29 20:21:46 -07:00
tangxifan 7723e00e6c [Engine] Adding the function that builds a shift register module for BL/WLs 2021-09-28 22:49:24 -07:00
tangxifan 2de4a460a8 [Engine] Rework the function that counts the number of configurable children for fabric key writer and bitstream generator 2021-09-24 15:15:32 -07:00
tangxifan 18257b3fa1 [Engine] Update BL/WL port addition for the top-level module in fabric generator 2021-09-24 11:07:58 -07:00
tangxifan 8c281a22b0 [Engine] Add check codes to validate circuit models for BL/WL protocols 2021-09-23 14:39:16 -07:00
tangxifan 962acda810 [Engine] Bug fix in fabric key generation when computing configurable children 2021-09-22 11:09:46 -07:00
tangxifan 36a4da863c [Engine] Support WLR port in OpenFPGA architecture file and fabric generator 2021-09-20 16:05:36 -07:00
tangxifan b787c4e100 [Engine] Register QL memory bank as a legal protocol 2021-09-09 15:06:51 -07:00
tangxifan 6f09f5f7ad [FPGA-Bitstream] Upgrade bitstream generator to support QL memory bank 2021-09-05 21:25:58 -07:00
tangxifan b83eef47b4 [Tool] Bug fix for testbench generation without self checking codes 2021-06-29 16:27:29 -06:00
tangxifan 6a260cadbf [Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose 2021-06-29 15:42:23 -06:00
tangxifan 7ac7de789e [Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes 2021-06-29 15:26:40 -06:00
tangxifan 991062e9bf [Tool] Bug fix 2021-06-25 15:22:42 -06:00
tangxifan 90163fab6c [Tool] Replace option '--support_icarus_simulator' with a new one '--preload_bitstream <string>' 2021-06-25 15:06:07 -06:00
tangxifan 2bb514c51a [Tool] Support time unit in writing simulation information file 2021-06-25 10:33:29 -06:00
tangxifan bcc16d732c [Tool] Add new option 'testbench_type' so that simulation task can write different information for different testbenches 2021-06-25 10:10:16 -06:00
tangxifan 5364d8104f [Tool] Add signal_init option to preconfigured fabric wrapper writer 2021-06-24 17:07:41 -06:00
tangxifan fed975c52a [Tool] Add postfix removal support in write_io_mapping command 2021-06-18 16:13:50 -06:00
tangxifan d9d57aad42 [Tool] Added default net type options to verilog testbench generator command 2021-06-14 11:37:49 -06:00
tangxifan 7ade48343c [Tool] Deprecate command 'write_verilog_testbench' 2021-06-09 17:06:01 -06:00
tangxifan 2299ce3157 [Tool] Preconfigured testbench writer now supports icarus simulator 2021-06-09 13:49:25 -06:00
tangxifan 3bc8e760db [Tool] Add '--fabric_netlist' option to 'write_preconfigured_testbench' command 2021-06-09 11:14:45 -06:00
tangxifan 89fb672631 [Tool] Fine-tune the options of 'write_simulation_task_info' to be straightforward to use 2021-06-09 10:49:00 -06:00
tangxifan 97396eda2b [Tool] Add a new command 'write_simulation_task_info' 2021-06-08 22:10:02 -06:00
tangxifan d2275b971d [Tool] Add a new command 'write_preconfigured_testbench' 2021-06-08 21:53:51 -06:00
tangxifan 8db19c7af9 [Tool] Add a new command 'write_preconfigured_fabric_wrapper' 2021-06-08 21:28:16 -06:00
tangxifan 061f832429 [Tool] Enable fast configuration when writing fabric bitstream 2021-06-04 16:23:40 -06:00
tangxifan 81048d3698 [Tool] Add option '--fast_configuration' to 'write_full_testbench' command 2021-06-04 11:26:39 -06:00
tangxifan ae6a46cd60 [Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique 2021-06-03 15:41:11 -06:00
tangxifan c4ecc9ee7c [Tool] Patch data type of report bitstream distribution command-line option 2021-05-07 11:44:01 -06:00
tangxifan db9bb9124e [Tool] Add report bitstream distribution command to openfpga shell 2021-05-07 11:41:25 -06:00
tangxifan 43c1e052ef [Tool] Add a writer to output I/O mapping information to XML files 2021-04-27 14:30:16 -06:00
tangxifan 56948244bc [Tool] Patch a critical bug in pb pin fixup 2021-04-22 16:19:54 -06:00
tangxifan 0aec30bac6 [Tool] Update FPGA core engine to support mux default path overloading through bitstream setting file 2021-04-19 15:53:33 -06:00
tangxifan c8d41b4e69 [Tool] Change routing module port naming to include architecture port names 2021-03-14 19:35:49 -06:00
tangxifan 956b9aca01 [Tool] Trim dead codes in port naming function 2021-03-13 20:23:08 -07:00
tangxifan 2c5634ee76 [Tool] Change pin naming of grid modules to be related to architecture port names 2021-03-13 20:05:18 -07:00
tangxifan 15e26a5602 [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00