only core0 is brought up by bootloader
Change-Id: I1d6b5e6ba7498beadbf3805f4271f0197e411bd5
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-on: http://openocd.zylin.com/5980
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
STM32L5 have 512 Kbytes of Flash memory with dual bank architecture.
STM32L5 flash is quite similar to L4 flash, mainly register names
and offsets and some bits are changed.
NON-SECURE flash is located at 0x8000000 like L4 devices, so no
big change is needed (secure flash will be subject of another change).
Note: flash driver name is set stm32l5x, in order to extend the commands
with specific L5 commands (to manage TZEN for example ...)
Note: this works only when TZEN=0
Change-Id: Ie758abb4aa19a3f29eeb0702d7dcb43992e4c639
Signed-off-by: Michael Jung <mijung@gmx.net>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5510
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
- write speed up to 150 kByte/s on STM32F469I-disco (due to
SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI
with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in
dual 4-line mode or STM32H73BI-Disco in octal mode
- tested with STM32L476G-disco (64MBit flash, 3-byte addr),
STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and
STM32L476G-Disco (all 128Mbit flash, 3-byte addr),
STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr)
STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr)
STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr)
STM32H73BI-Disco, STM32H735G-Disco (512MBit octo-flash, DTR, 4-byte addr)
- suitable cfg for Discovery boards included
- limited parsing of SFDP data if flash device not hardcoded
(tested only in single/quad mode as most devices either don't
support SFDP at all or have empty(!) SFDP memory)
- 'set' command for auto detection override (e. g. for EEPROMs)
- 'cmd' command for arbitrary SPI commands (reconfiguration, testing etc.)
- makefile for creation of binary loader files
- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg
- tcl/board/stm32f7discovery.cfg removed as name is ambiguous
(superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg)
- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q
with two W25Q256FV, and on Nucleo-L496ZP-P and Nucleo-L4R5ZI
with two W25Q128FV, sample cfg files included and on STM32H745I-Disco,
STM32H747I-Disco, STM32H750B-Disco
- read/verify/erase_check uses indirect read mode to work around silicon bug in
H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last
bytes causes debug interface to hang)
- octospi supported only in single/dual 1-line, 2-line, 4-line
and single 8-line modes, (not in hyper flash mode)
Requirements:
GPIOs must be initialized appropriately, and SPI flash chip be configured
appropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip
specific, cf. included cfg files. The driver infers most parameters from
current setting in CR, CCR, ... registers.
Change-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4321
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>
regsub doesn't work correctly on macOS Catalina, which results in
an incorrect CHIPNAME derived from the current target. Since regsub
is only used by this target, replace it with a simple string search
for '.' followed by a substring. This is funcionally equivalent to
what the regular expression was doing, but instead relies in simpler
string operations that should have little to no differences
between systems.
Also, refactor CHIPNAME detection into proc stm32h7x_chipname, so
it's always retrieved in the same way without duplicating the code.
Change-Id: Ia9f63f56b508688e74278b022eaec47e503916e7
Signed-off-by: Alberto Garcia Hierro <alberto@garciahierro.com>
Reviewed-on: http://openocd.zylin.com/5872
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
in RM0399 rev2, there was these bits in DBGMCU_CR registers:
- DBGSTBY_D3 : bit 7
- DBGSTOP_D3 : bit 8
these bits have been changed to reserved in rev3
Change-Id: I9d10d90e383795dc8e25a117d59fa065dc594610
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5861
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
nrf52_recover was merged in pre "Handle Tcl return values consistently"
state - remove ocd_ prefixes.
Erase and unlock sequence was changed to comply Nordic semiconductor
recommendation:
https://infocenter.nordicsemi.com/index.jsp?topic=%2Fnwp_027%2FWP%2Fnwp_027%2FnWP_027_erasing.html
Change-Id: Ic54236c27cf25ad8091e9e572ba1ef846f0d47c2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reported-by: Pieter De Gendt <pieter.degendt@gmail.com>
Reviewed-on: http://openocd.zylin.com/5845
Tested-by: jenkins
Reviewed-by: Pieter De Gendt <pieter.degendt@gmail.com>
Used histogram diff strategy, which was much better than the default.
Conflicts:
doc/openocd.texi
src/flash/nor/fespi.c
src/jtag/drivers/libjaylink
src/rtos/rtos.c
src/target/riscv/batch.c
src/target/riscv/encoding.h
src/target/riscv/riscv-011.c
src/target/riscv/riscv-013.c
src/target/riscv/riscv.c
src/target/riscv/riscv.h
src/target/target.c
tcl/target/gd32vf103.cfg
Change-Id: I1321f62ba719419e58f93b2195f2540bd62f50d2
* riscv: work around buggy hart states during reset in some DMs
As described in the comment this change adds, the GD32VF103 DM reports
that the hart is in more than one state while it is resetting. Because
of this, the current code acknowledges resets before they actually
complete. This sometimes prevents havereset from getting cleared as
intended, leading to a spurious "Hart 0 unexpectedly reset!" message the
next time riscv_is_halted() gets called.
To work around this, check for the absence of the unavailable state
rather than the presence of the running or halted states. This behavior
is also arguably more true to the spec than what exists now: Section 3.2
states that "The system may take an arbitrarily long time to come out of
reset, as reported by allunavail, anyunavail."
Change-Id: I34e90a16233125608bce8e4c2414dbead637600e
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
* riscv: support custom reset-assert scripts
The reset-assert event is used, if present, to override the default
reset logic for ARM and MIPS cores. Do the same for RISC-V so that
devices with buggy ndmreset functionality (like GD32VF103) or
nonstandard reset sequences can specify the appropriate logic in Tcl.
Change-Id: I5e12077d67509853edb8ef3ad3f037f293a5fbb6
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
* tcl/target: support GD32VF103 RISC-V MCU
The GD32VF103 is a low-cost 32-bit RISC-V microcontroller with
peripherals that are more-or-less compatible with the STM32F103 ARM
microcontroller. It is available on several low-cost dev boards, such as
the Sipeed Longan Nano, which is what I am testing on.
Add initial support for this chip, including a workaround for a buggy
ndmreset line (i.e. one that doesn't actually trigger a reset) in its
integrated debug module. Use the existing GD32VF103 flash driver that
was ported from the vendor's code in commit 48e40f3513 ("Add support
for GD32VF103 flash").
Change-Id: Iadac47ceb5437b8e18f3d35901388f10fef9f876
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
* tcl/target/gd32vf103: add main flash alias
The GD32VF103 creates an alias to either main flash or the bootloader at
0x0, depending on how it was booted. As such, we want to indicate to
debuggers that the memory at 0x0 is flash and so cannot support software
breakpoints. To do this, add an alias to the main flash in the config.
This isn't strictly accurate in the case where we're running the
bootloader, but it still suits our purpose of fixing breakpoint
behavior.
Change-Id: I9eb8462d354f096eee231c0e5e2bffa538a5903e
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
All the HLA transports (hla_swd and hla_jtag) register the same
set of commands. Such commands are mainly aimed at handling JTAG
compatibility that is required for the transport hla_jtag only.
Split per transport the command registration and limit the
commands to only those required by the transport itself.
Replace the command "hla newtap" with the transport specific
"swd newdap" or "jtag newtap".
Deprecate the command "hla".
Change-Id: I79c78fa97b707482608516d3824151a4d07644c0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4877
Tested-by: jenkins
A JTAG TAP for boundary scan should be added in the scan chain
through the command "jtag newtap".
In some TCL target script the boundary scan TAP is added through
the command "swj_newdap", command that is inappropriate in this
context because specific for arm adi-v5 SWJ-DP.
This situation was probably created to bypass the error with HLA
framework, caused by missing command "jtag newtap".
Add the command "jtag newtap" in HLA, by reusing the existing
code for command "hla newtap".
Fix the TCL target scripts to use the command "jtag newtap" for
the boundary scan TAPs.
The TCL script target/psoc6.cfg has no evident reference to HLA,
so the reason for using "swj_newdap" is less clear. Nevertheless
it uses the wrong command and, once HLA is fixed, there is no
reason to avoid fixing it too.
Change-Id: Ia92f8221430cf6f3d2c34294e22e5e18963bb88c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4873
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The "Corvette-F1" is an Arduino-compatible evaluation platform,
which fully supports AndesCore. The board has FTDI FT2232 to
connected to FPGA's JTAG interface.
The "ADP-XC7KFF676" is a development and prototyping board that
provides capacity for evaluation of AndesCore processors.
It works with AICE in-circuit debugging tools.
This patch also include target/nds32v5.cfg to support AndesCore
N22/N25F and AndeShape Platform AE250.
Change-Id: I144d5063d5086d00ec44634a5028b5ea5d2eba33
Signed-off-by: Hellosun Wu <wujiheng.tw@gmail.com>
Reviewed-on: http://openocd.zylin.com/5338
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
As the comment states, the 'init' command is issued before the
command 'dap apsel', otherwise it fails.
This dependency has been already fixed in commit e48690cb26
("target/arm_adi_v5: allow commands apsel and apcsw during init
phase"), so the command 'dap apsel' can now be issued directly.
Remove both the unneeded 'init' command and the comment that
documents and justify its presence.
Change-Id: I50f0a820fa7ead6f5a3bd9cc5180d521070822c9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5786
Tested-by: jenkins
There is no flash bank support at the moment.
Change-Id: I52a2bde39425d94d9333cda002e5df0a1ef63c08
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/5755
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
With this commit we add tcl configure files
for ARCv2 HS Development kit(HSDK). HSDK board
has Quad-core ARC HS38 CPU with L1 and L2
caches.
Change-Id: I372ef45428c7c7ca1421a6da3e5ed08b86f705e0
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5784
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
In addition to the debug TAPs, the ICEPick C also supports
a bank of Test TAPs (limited functionality intended for
non-debuggable targets). Added support for Test TAPs to
the icepick_c_tapenable routine. Port numbers of 0 to 15
will continue to be handled as a debug TAP number. Test
TAPs will be port numbers of 16 to 31.
This functionality will be needed for doing a flash
mass erase on CC26xx/CC13xx targets. It is possible
for user application to block even adding the Cortex M
TAP to the scan chain, so the only way to unbrick the
target and erase the flash is using a component on a
test TAP of the device's ICEPick router.
Change-Id: I0aa52a08d43a00cbd396efdeadd504fc31c98510
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5715
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Previously the adapter speed settings were hard-coded to
connect with low speed then switch over to high speed
regardless what was mentioned in the cfg files. Now the
stm8 target intercept adapter speed settings and configure
the stm8 control registers accordingly.
Change-Id: I7419514e5214e4b43b9d51253cf5b7f04a233533
Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com>
Reviewed-on: http://openocd.zylin.com/5548
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add SWIM and STM8 to documentation and update TODO file.
Introduce transport "swim" and command "swim newtap".
Switch in swim.c from HLA API to the new SWIM API.
Implement in stlink driver the SWIM APIs as wrappers of existing
HLA functions.
Remove any SWIM related reference from HLA files.
Update stm8 config files and stlink-dap interface config file.
Change-Id: I2bb9f58d52900f6eb4df05f979f7ef11fd439c24
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5530
Tested-by: jenkins
SWIM transport only supports two adapter speeds:
- "low speed" equal to 363 kHz (8 MHz / 22)
- "high speed" equal to 800 kHz (8 MHz / 10)
Replace the previous convention that use "0" or "1" for "low" or
"high" speed with the effective speed in kHz.
Rework the implementation of stlink_speed_swim().
Set low speed in the stm8 config files, because only low speed is
permitted at debug connection; the previous code ignores the
initial value.
Change-Id: I2484c9419a2c554c59eb6b9216339393ab0b54f3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5529
Tested-by: jenkins
The script checkpatch available in new Linux kernel offers an
experimental feature for automatically fix the code in place.
While still experimental, the feature works quite well for simple
fixes, like spacing.
This patch has been created automatically with the script under
review for inclusion in OpenOCD, using the command:
find tcl/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types TRAILING_WHITESPACE --fix-inplace -f {} \;
The patch only changes amount and position of whitespace, thus
the following commands show empty diff
git diff -w
git log -w -p
git log -w --stat
Change-Id: Ie7e3a236f4db9c70019e3b3c7e851edbd3a9dd84
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5616
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Identified by checkpatch script from Linux kernel v5.7-rc1 using
the command
find tcl/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types TYPO_SPELLING --strict -f {} \;
Change-Id: I7b523f0ab5ec047ff167742a44c29984ac672cf4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5615
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
The state machine of cortex-m have to pass through a set of state
before it get in "halted".
Add one more "arp_poll" to achieve the proper state during a
"reset halt" command in engineering boot.
Change-Id: I90828bf20ef75bd4018f8b911f727ae69c4d6e8f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5649
Tested-by: jenkins
Reviewed-by: Richard Braun <rbraun@sceen.net>
Empty lines at end of text files are useless.
Remove them.
Change-Id: I503cb0a96c7ccb132f4486c206a48831121d7abd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5171
Tested-by: jenkins
This commits adds debugging support for the Mellanox BlueField
SoC via rshim, which is an interface accessible from external USB
or PCIe (for SmartNIC case) via the rshim driver. It implements
the arm dap interfaces based on the existing dapdirect framework.
Change-Id: I18eb1c54293ec2c581f853e0e55b3f96d7978b56
Signed-off-by: Liming Sun <lsun@mellanox.com>
Reviewed-on: http://openocd.zylin.com/5457
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The stm32mp15x has one or two Cortex-A7 (depending on the P/N) and
one Cortex-M4.
The second core is automatically detected by the target script.
In "engineering boot" all the cores are accessible.
In "production boot" the Cortex-M4 is kept in reset state after
power-on or NRST.
The board DK2 includes a ST-Link/V2, but only SWD is connected.
Change-Id: Ib6ebefcc696b1716e0f98694cadf0b04fd7d11d6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5454
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
With this commit we add tcl files which describes
ARCv2 architecture features and configure files
for ARCv2 EMSK board.
Changes since v1:
-Moved from http://openocd.zylin.com/#/c/5332/4
into separate commit.
Changes:
22.01.2020:
-Removed "actionpoints" handling code in
tcl/cpu/arc/v2.tcl because this capability
is not supported yet.
Changes:
17.03.2020:
-Update Licence headers
-Cleanup indents
-Removed "reset halt" in boards .tcl
-Updated adapter frequency commands
Changes:
15.03.2020:
-Removed "init" in the of boards .tcl
Change-Id: I51bf620abe7b8e046e1dccc861a7d963965d3a42
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5350
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
nSRST and sysreqreset are both broken for these targets. Upon a
hard reset, the target disables the TDO/TDI pins and the
ICEPick router will remove the target's TAP from the scan
chain. The scripts to do these tasks are run, but then
OpenOCD throws the reset again breaking the debug connection.
Until that issue can be resolved, vectreset is the only
reset that works without breaking the debug connection.
Update: original patch didn't have the correct reset command.
Change-Id: If7c985b703c87399a13364609d370d6222f4a66c
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5511
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
On CC32xx family of devices, sysrequest is disabled, and
vectreset is blocked by the boot loader (stops in a while(1)
statement). srst reset can leave the target in a state
that prevents debug.
This change enables using vectreset on SF variants by
moving the PC to the start of the user application in
internal flash. This allows for a more reliable reset,
but with two caveats:
1) This only works for the SF variant with internal
flash.
2) This only resets the CPU and not any peripherals.
Tested on CC3220SF rev B Launchpad in both SWD and
JTAG modes. Confirmed proper behavior of reset,
reset init, reset halt, and reset run commands.
Update: reworked per comment in code review. Re-tested
with CC3220SF Launchpad as both CC3220SF and as
CC32xx board to confirm reset behavior as expected.
Update: Added adapter srst delay 1100 line to the
CC3200 LaunchXL configuration file.
Change-Id: Ibc042d785c846c2223ae55b8f2410b75ed2df354
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5489
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Confirmed that sysresetreq is supported and works better
for MSP432P4 and MSP432E4 targets than srst that was
previously being used.
Tested on MSP432P4111, MSP432P401R, and MSP432E401Y
Launchpads.
Change-Id: I1454c3379b9300bc133f82a766daeaefb98dbaac
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5488
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
STM32WLEx devices are based on arm Cortex-M4 running at 48MHz,
contains a single bank of maximum 256 Kbytes of flash memory.
there is 3 variants with different Flash/RAM sizes:
STM32WLE5JC : 256K/64K
STM32WLE5JB : 128K/48K
STM32WLE5J8 : 64K/20K
the work-area size is set to 20 kb to fit in STM32WLE5J8
Change-Id: Ie8e186fe4be97cbc25c53ef0ade4b4dbbcee6f66
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5450
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Flash module of STM32G0/G4 family is quite similar to the one of
STM32L4, so only minor changes are required, in particular
adaption of flash loader to Cortex-M0. Register addresses
passed to flash loader to simplify integration of L5.
Added re-probe after option byte load.
Added flash size override via cfg file.
WRPxxR mask now based on max. number of pages instead of fixed 0xFF,
as G4 devices fill up unused bits with '1'.
Sizes in stm32l4_probe changed to multiples of 1kB.
Tested with Nucleo-G071RB, G030J6, Nucleo-G431RB and Nucleo-G474RE.
Gap handling in G4 Cat. 3 dual bank mode tested with STM32G473RB.
This handling isn't optimal as the bank size includes the
size of the gap. WB not tested.
Change-Id: I24df7c065afeb71c11c7e96de4aa9fdb91845593
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4807
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The RZ/A1 is not part of the R-Car family, but is rather an RZ family.
Fix the naming.
Change-Id: I5f882b2467e87e534e0f1c827554e664a7d55664
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5445
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
A configuration script may want to check the reason why examine fails
e.g. device has security lock engaged.
tcl/target/kx.cfg and klx.cfg is modified to use the new event
for testing of the security lock of Kinetis MCU
Change-Id: Id1d3a79d24e84b513f4ea35586cd2ab0437ff9b3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4289
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Change-Id: I693e5b7933fc61956010a96be57ee6eb8abd3c31
Signed-off-by: Anton V. Kirilchik <kosmonaffft@gmail.com>
Reviewed-on: http://openocd.zylin.com/5422
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Both Gen2 and Gen3 used the same init_reset{} implementation,
pull it into common file and include it from both generations.
Moreover, this behavior is SoC specific, not board specific,
so move the common init_reset into target/ directory.
Change-Id: I5489a4bff9a786da8cb7fd7a515b0c9ce9dc16e3
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5400
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Adopted only fast algorithm for flash programming:
- write_word and write_byte methods have been removed.
- start and end write alignments have been defined.
Moved flash controller registers offsets in a common file
shared with the flash algorithm.
- the flash base address is passed to the flash algorithm
as a parameter.
Removed unused functions
Change-Id: I80aeab3994e477044bbcf02e66d9525dae0cb491
Signed-off-by: luca vinci <luca.vinci@st.com>
Reviewed-on: http://openocd.zylin.com/5393
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Michele Sardo <msmttchr@gmail.com>
Drop old Renesas Gen2 SoC configurations, as they were superseded by
the new unified config.
Change-Id: I7c2ccbdc13b01a552ce9cafdc1538f226beaa9f2
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5399
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Add configuration for the Renesas R-Car Generation 2 targets.
These are SoCs with Cortex A15s and A7s. All cores currently
supported by OpenOCD are supported here as well as two new
cores, M2N and V2H, for the sake of support completeness.
Change-Id: Ib6fe70a91360b4f8bd69822ee28b6dea530cfa0a
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5397
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Some text file is missing newline at EOF.
Add it.
Change-Id: Ieebc790096f40961283c644642e56fde975e957f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5167
Tested-by: jenkins
Change-Id: Ib452435b13c3cb8d14453d983151936238b9601d
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/5419
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Some script have been added or modified after the patches for
reworking the adapter commands were pushed in gerrit.
Such scripts use the old command syntax and trigger a "deprecated"
warning at runtime.
Fix them with the same sed commands used for the other scripts:
sed -i 's/^interface /adapter driver /' $(find tcl/ -type f)
sed -i 's/adapter_khz/adapter speed/g' $(find tcl/ -type f)
sed -i 's/adapter_nsrst_delay/adapter srst delay/g' $(find tcl/ -type f)
sed -i 's/adapter_nsrst_assert_width/adapter srst pulse_width/g' $(find tcl/ -type f)
Change-Id: I0824d6c506a9af3eb9129b74c02a92b4eb1b100d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5424
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
Tim Newsome
Jiri Kastner
Tarek BOCHKATI
Tarek BOCHKATI
Andreas Bolsch
Alberto García Hierro
Antonio Borneo
Tomas Vanek
Jan Kowalewski
Tom Hebb
Hellosun Wu
Marc Schink
Evgeniy Didin
Edward Fewell
Ake Rehnman
Liming Sun
Marek Vasut
Anton V. Kirilchik
luca vinci