tcl: fix typo and spelling
Identified by checkpatch script from Linux kernel v5.7-rc1 using
the command
find tcl/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types TYPO_SPELLING --strict -f {} \;
Change-Id: I7b523f0ab5ec047ff167742a44c29984ac672cf4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5615
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
This commit is contained in:
Antonio Borneo
parent
3a28cdc7cb
commit
6d3cb807aa
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@ -23,7 +23,7 @@ $_TARGETNAME configure -event reset-init {
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# select PLL as main source
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mww 0x80040120 0x1
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# disable and enble main clk to update changes?
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# disable and enable main clk to update changes?
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mww 0x80040124 0x0
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mww 0x80040124 0x1
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@ -169,7 +169,7 @@ proc at91sam9g20_reset_init { } {
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# TRC = 9 cycles
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# TWR = 2 cycles
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# 9 column, 13 row, 4 banks
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# refresh equal to or less then 7.8 us for commerical/industrial rated devices
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# refresh equal to or less then 7.8 us for commercial/industrial rated devices
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#
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# Thus SDRAM_CR = 0xa6339279
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@ -22,7 +22,7 @@ jtag_rclk 1000
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$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
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$_TARGETNAME configure -event "reset-assert" {
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echo "Reseting ...."
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echo "Resetting ...."
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#cortex_a dbginit
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}
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@ -170,11 +170,11 @@ proc imx35pdk_init { } {
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mww 0xB8001010 0x00000304
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#--------------------------------------------
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# Init 32-bit DDR2 memeory on CSD0
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# Init 32-bit DDR2 memory on CSD0
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# COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
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#--------------------------------------------
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# ESD_ESDCFG0 : set timing paramters
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# ESD_ESDCFG0 : set timing parameters
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mww 0xB8001004 0x007ffC2f
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# ESD_ESDCTL0 : select Prechare-All mode
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@ -21,7 +21,7 @@ reset_config trst_and_srst separate trst_open_drain srst_open_drain
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adapter speed 6000
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$_TARGETNAME configure -event "reset-assert" {
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echo "Reseting ...."
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echo "Resetting ...."
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#cortex_a dbginit
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}
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@ -23,7 +23,7 @@ $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
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#jtag_ntrst_delay 200
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$_TARGETNAME configure -event "reset-assert" {
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echo "Reseting ...."
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echo "Resetting ...."
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#cortex_a dbginit
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}
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@ -162,7 +162,7 @@ proc kindle2_sdram_init {} {
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# LPDDR1 Initialization script
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mww 0xb8001010 0x00000002
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mww 0xb8001010 0x00000004
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# ESDCFG0: set timing paramters
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# ESDCFG0: set timing parameters
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mww 0xb8001004 0x007fff7f
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# ESDCTL0: select Prechare-All mode
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mww 0xb8001000 0x92100000
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@ -1,7 +1,7 @@
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#
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# Sony Ericsson J100I Phone
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#
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# more informations can be found on
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# more information can be found on
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# http://bb.osmocom.org/trac/wiki/SonyEricssonJ100i
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#
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source [find target/ti_calypso.cfg]
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@ -9,7 +9,7 @@
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#
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# Configure JTAG cable
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# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
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# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
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source [find interface/ftdi/digilent-hs1.cfg]
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# 5MHz seems to work good with all cores that might happen in 2.x
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@ -9,7 +9,7 @@
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#
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# Configure JTAG cable
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# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
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# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
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source [find interface/ftdi/digilent-hs1.cfg]
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adapter speed 10000
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@ -9,7 +9,7 @@
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#
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# Configure JTAG cable
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# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
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# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
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source [find interface/ftdi/digilent-hs1.cfg]
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# JTAG 10MHz is too fast for EM7D FPU in EM SK 2.1 which has core frequency
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@ -9,7 +9,7 @@
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#
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# Configure JTAG cable
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# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
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# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
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source [find interface/ftdi/digilent-hs1.cfg]
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# EM11D reportedly requires 5 MHz. Other cores and board can work faster.
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@ -1,5 +1,5 @@
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# Use for the STM207VG plug-in board (1 MiB Flash and 112+16 KiB Ram
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# comming with the STEVAL-PCC010 board
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# coming with the STEVAL-PCC010 board
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# http://www.st.com/internet/evalboard/product/251530.jsp
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# or any other board with only a STM32F2x in the JTAG chain
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@ -1,5 +1,5 @@
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source [find target/c100.cfg]
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# basic register defintion for C100
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# basic register definition for C100
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source [find target/c100regs.tcl]
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# board-config info
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source [find target/c100config.tcl]
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@ -30,7 +30,7 @@ proc topas910_init { } {
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# Init SDRAM
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# _PMCDRV = 0x00000071;
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# //
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# // Initialize SDRAM timing paramater
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# // Initialize SDRAM timing parameter
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# //
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# _DMC_CAS_LATENCY = 0x00000006;
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# _DMC_T_DQSS = 0x00000000;
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@ -37,7 +37,7 @@ proc topasa900_init { } {
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# Init SDRAM
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# _PMCDRV = 0x00000071;
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# //
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# // Initialize SDRAM timing paramater
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# // Initialize SDRAM timing parameter
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# //
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# _DMC_CAS_LATENCY = 0x00000006;
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# _DMC_T_DQSS = 0x00000000;
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@ -5,7 +5,7 @@
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source [find target/k60.cfg]
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$_TARGETNAME configure -event reset-init {
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puts "-event reset-init occured"
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puts "-event reset-init occurred"
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}
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#
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@ -5,7 +5,7 @@
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source [find target/k60.cfg]
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$_TARGETNAME configure -event reset-init {
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puts "-event reset-init occured"
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puts "-event reset-init occurred"
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}
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#
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@ -5,7 +5,7 @@
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# voltages. The XADC is available both from fabric as well as through the
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# JTAG TAP.
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#
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# This code implements access throught the JTAG TAP.
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# This code implements access through the JTAG TAP.
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#
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# https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
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@ -15,7 +15,7 @@ ftdi_vid_pid 0x0403 0x6014
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ftdi_layout_init 0x0030 0x003b
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# 0xfff8 0xfffb
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# Those signal are only required on some platforms or may required to be
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# enabled explicitely (e.g. nrf5x chips).
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# enabled explicitly (e.g. nrf5x chips).
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ftdi_layout_signal nSRST -data 0x0010 -oe 0x0010
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ftdi_layout_signal nTRST -data 0x0020 -oe 0x0020
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@ -28,7 +28,7 @@ proc show_mmr32_reg { NAME } {
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}
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# Give: NAMES - an array of names accessable
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# Give: NAMES - an array of names accessible
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# in the callers symbol-scope.
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# VAL - the bits to display.
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@ -10,7 +10,7 @@ if { [info exists CHIPNAME] } {
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set _CHIPNAME aducm360
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}
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# Endianess
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# Endianness
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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@ -28,7 +28,7 @@ if { $_CPUTAPID == 0x15b0203f } {
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echo "- ERROR: -"
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echo "- ERROR: In one position (0x05b0203f) it selects the -"
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echo "- ERROR: ARM CPU, in the other position (0x1b0203f) -"
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echo "- ERROR: it selects boundry-scan not the ARM -"
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echo "- ERROR: it selects boundary-scan not the ARM -"
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echo "- ERROR: -"
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echo "-------------------------------------------------------"
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}
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@ -1,5 +1,5 @@
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# board(-config) specfic parameters file.
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# board(-config) specific parameters file.
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# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
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proc config {label} {
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@ -15,7 +15,7 @@ proc helpC100 {} {
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echo "12) ooma_board_detect: will show which version of Telo you have"
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echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configureg"
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echo "14) showDDR2: will show DDR2 config registers"
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echo "15) showWatchdog: will show current regster config for watchdog"
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echo "15) showWatchdog: will show current register config for watchdog"
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echo "16) reboot: will trigger watchdog and reboot Telo (hw reset)"
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echo "17) bootNOR: will boot Telo from NOR"
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echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be confiured"
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@ -176,7 +176,7 @@ proc setupAmbaClk {} {
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mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
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mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
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# wait for PLL to lock
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echo "Wating for Amba PLL to lock"
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echo "Waiting for Amba PLL to lock"
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while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 }
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# remove the internal PLL bypass
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mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
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@ -250,7 +250,7 @@ proc setupArmClk {} {
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mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
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mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
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# wait for PLL to lock
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echo "Wating for Amba PLL to lock"
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echo "Waiting for Amba PLL to lock"
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while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 }
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# remove the internal PLL bypass
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mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
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@ -300,7 +300,7 @@ proc setupDDR2 {} {
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# Memory setup register
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mww $MEMORY_MAX_ADDR [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR]
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# disbale ROM remap
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# disable ROM remap
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mww $MEMORY_CR 0x0
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# Take DDR controller out of reset
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mmw $BLOCK_RESET_REG $DDR_RST 0x0
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@ -486,7 +486,7 @@ proc reboot {} {
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set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
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# allow the counter to count to high value before triggering
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# this is because regsiter writes are slow over JTAG and
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# this is because register writes are slow over JTAG and
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# I don't want to miss the high_bound==curr_count condition
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mww $TIMER_WDT_HIGH_BOUND 0xffffff
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mww $TIMER_WDT_CURRENT_COUNT 0x0
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@ -494,7 +494,7 @@ proc reboot {} {
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adapter speed 100
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mww $TIMER_WDT_CONTROL 0x1
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# wait until the reset
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echo -n "Wating for watchdog to trigger..."
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echo -n "Waiting for watchdog to trigger..."
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#while {[mrw $TIMER_WDT_CONTROL] == 1} {
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# echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
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# sleep 1
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@ -35,7 +35,7 @@ set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME
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# Setup the interesting tap
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# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations requiere certain instruction to be in the IR register during reset, and polling would change this)
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# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations require certain instruction to be in the IR register during reset, and polling would change this)
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jtag configure $_CHIPNAME.chp -event setup "
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jtag tapenable $_TARGETNAME
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poll off
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@ -14,7 +14,7 @@ if { [info exists CPUTAPID] } {
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if { [info exists HAS_ETB] } {
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} else {
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# Set default (no ETB).
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# Show a warning, because this should have been configured explicitely.
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# Show a warning, because this should have been configured explicitly.
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set HAS_ETB 0
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# TODO: warning?
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}
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@ -22,7 +22,7 @@ if { [info exists CPUTAPID] } {
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}
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# Scan Tap
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# Wired to seperate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module
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# Wired to separate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module
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# JTAGSEL pin must be 0 to activate, which reassigns arm tdo to a pass through.
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if { [info exists SJCTAPID] } {
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set _SJCTAPID $SJCTAPID
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@ -164,7 +164,7 @@ $_TARGETNAME configure -event reset-start {
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} else {
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if {![using_hla]} {
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# Tempest and Firestorm default to using NVIC VECTRESET
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# peripherals will need reseting manually, see proc reset_peripherals
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# peripherals will need resetting manually, see proc reset_peripherals
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cortex_m reset_config vectreset
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}
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# reset peripherals, based on code in
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@ -25,7 +25,7 @@ proc ocd_process_reset_inner { MODE } {
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soft_reset_halt
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# Intialize MSP, PSP, and PC from vector table at flash 0x01000800
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# Initialize MSP, PSP, and PC from vector table at flash 0x01000800
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mem2array boot 32 0x01000800 2
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reg msp $boot(0)
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@ -38,7 +38,7 @@ openocd -f interface/ftdi/tumpa.cfg -f tools/firmware-recovery.tcl \\
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shutdown
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}
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# set default, can be overriden later
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# set default, can be overridden later
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adapter speed 1000
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proc get_partition { name } {
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