Introduce ARCv2 tcl config files
With this commit we add tcl files which describes ARCv2 architecture features and configure files for ARCv2 EMSK board. Changes since v1: -Moved from http://openocd.zylin.com/#/c/5332/4 into separate commit. Changes: 22.01.2020: -Removed "actionpoints" handling code in tcl/cpu/arc/v2.tcl because this capability is not supported yet. Changes: 17.03.2020: -Update Licence headers -Cleanup indents -Removed "reset halt" in boards .tcl -Updated adapter frequency commands Changes: 15.03.2020: -Removed "init" in the of boards .tcl Change-Id: I51bf620abe7b8e046e1dccc861a7d963965d3a42 Signed-off-by: Evgeniy Didin <didin@synopsys.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5350 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
This commit is contained in:
Evgeniy Didin
Oleksij Rempel
parent
a1c51caafb
commit
435e6101c6
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# Copyright (C) 2014-2016,2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Synopsys DesignWare ARC EM Starter Kit v2.x
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#
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# Configure JTAG cable
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# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
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source [find interface/ftdi/digilent-hs1.cfg]
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# 5MHz seems to work good with all cores that might happen in 2.x
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adapter speed 5000
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# ARCs support only JTAG.
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transport select jtag
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# Configure FPGA. This script supports both LX45 and LX150.
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source [find target/snps_em_sk_fpga.cfg]
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# Copyright (C) 2014-2016,2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Synopsys DesignWare ARC EM Starter Kit v1.0 and v1.1
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#
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# Configure JTAG cable
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# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
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source [find interface/ftdi/digilent-hs1.cfg]
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adapter speed 10000
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# ARCs support only JTAG.
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transport select jtag
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# Configure FPGA. This script supports both LX45 and LX150.
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source [find target/snps_em_sk_fpga.cfg]
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# Copyright (C) 2014-2016,2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Synopsys DesignWare ARC EM Starter Kit v2.1
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#
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# Configure JTAG cable
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# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
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source [find interface/ftdi/digilent-hs1.cfg]
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# JTAG 10MHz is too fast for EM7D FPU in EM SK 2.1 which has core frequency
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# 20MHz. 7.5 MHz seems to work fine.
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adapter speed 7500
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# ARCs support only JTAG.
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transport select jtag
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# Configure FPGA. This script supports both LX45 and LX150.
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source [find target/snps_em_sk_fpga.cfg]
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# Copyright (C) 2016,2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Synopsys DesignWare ARC EM Starter Kit v2.2
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#
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# Configure JTAG cable
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# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
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source [find interface/ftdi/digilent-hs1.cfg]
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# EM11D reportedly requires 5 MHz. Other cores and board can work faster.
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adapter speed 5000
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# ARCs support only JTAG.
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transport select jtag
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# Configure FPGA. This script supports both LX45 and LX150.
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source [find target/snps_em_sk_fpga.cfg]
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# Copyright (C) 2015, 2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Things common to all ARCs
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# It is assumed that target is already halted.
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proc arc_common_reset { {target ""} } {
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if { $target != "" } {
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targets $target
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}
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halt
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# 1. Interrupts are disabled (STATUS32.IE)
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# 2. The status register flags are cleared.
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# All fields, except the H bit, are set to 0 when the processor is Reset.
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arc jtag set-aux-reg 0xA 0x1
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# 3. The loop count, loop start, and loop end registers are cleared.
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arc jtag set-core-reg 60 0
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arc jtag set-aux-reg 0x2 0
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arc jtag set-aux-reg 0x3 0
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# Program execution begins at the address referenced by the four byte reset
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# vector located at the interrupt vector base address, which is the first
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# entry (offset 0x00) in the vector table.
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set int_vector_base [arc jtag get-aux-reg 0x25]
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set start_pc ""
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mem2array start_pc 32 $int_vector_base 1
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arc jtag set-aux-reg 0x6 $start_pc(0)
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# It is OK to do uncached writes - register cache will be invalidated by
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# the reset_assert() function.
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}
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# vim:expandtab:
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# Copyright (C) 2015, 2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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source [find cpu/arc/v2.tcl]
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proc arc_em_examine_target { {target ""} } {
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# Will set current target
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arc_v2_examine_target $target
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}
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proc arc_em_init_regs { } {
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arc_v2_init_regs
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[target current] configure \
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-event examine-end "arc_em_examine_target [target current]"
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}
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# Scripts in "target" folder should call this function instead of direct
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# invocation of arc_common_reset.
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proc arc_em_reset { {target ""} } {
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arc_v2_reset $target
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# Set DEBUG.ED bit to enable clock in actionpoint module.
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# This is specific to ARC EM.
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set debug [arc jtag get-aux-reg 5]
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if { !($debug & (1 << 20)) } {
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arc jtag set-aux-reg 5 [expr $debug | (1 << 20)]
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}
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}
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# Copyright (C) 2015, 2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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source [find cpu/arc/common.tcl]
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# Currently 'examine_target' can only read JTAG registers and set properties -
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# but it shouldn't write any of registers - writes will be cached, but cache
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# will be invalidated before flushing after examine_target, and changes will be
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# lost. Perhaps that would be fixed later - perhaps writes shouldn't be cached
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# after all. But if write to register is really needed from TCL - then it
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# should be done via "arc jtag" for now.
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proc arc_v2_examine_target { {target ""} } {
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# Set current target, because OpenOCD event handlers don't do this for us.
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if { $target != "" } {
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targets $target
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}
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# Those registers always exist. DEBUG and DEBUGI are formally optional,
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# however they come with JTAG interface, and so far there is no way
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# OpenOCD can communicate with target without JTAG interface.
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arc set-reg-exists identity pc status32 bta debug lp_start lp_end \
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eret erbta erstatus ecr efa
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# 32 core registers
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arc set-reg-exists \
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r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 \
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r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 \
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gp fp sp ilink r30 blink lp_count pcl
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# DCCM
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set dccm_version [arc get-reg-field dccm_build version]
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if { $dccm_version == 3 || $dccm_version == 4 } {
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arc set-reg-exists aux_dccm
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}
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# ICCM
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if { [arc get-reg-field iccm_build version] == 4 } {
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arc set-reg-exists aux_iccm
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}
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# MPU
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if { [arc get-reg-field mpu_build version] >= 2 &&
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[arc get-reg-field mpu_build version] <= 4 } {
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arc set-reg-exists mpu_en mpu_ecr
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set mpu_regions [arc get-reg-field mpu_build regions]
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for {set i 0} {$i < $mpu_regions} {incr i} {
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arc set-reg-exists mpu_rdp$i mpu_rdb$i
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}
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# Secure MPU
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if { [arc get-reg-field mpu_build version] == 4 } {
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arc set-reg-exists mpu_index mpu_rstart mpu_rend mpu_rper
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}
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}
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}
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proc arc_v2_init_regs { } {
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# XML features
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set core_feature "org.gnu.gdb.arc.core.v2"
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set aux_min_feature "org.gnu.gdb.arc.aux-minimal"
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set aux_other_feature "org.gnu.gdb.arc.aux-other"
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# Describe types
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# Types are sorted alphabetically according to their name.
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arc add-reg-type-struct -name ap_build_t -bitfield version 0 7 \
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-bitfield type 8 11
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arc add-reg-type-struct -name ap_control_t -bitfield at 0 3 -bitfield tt 4 5 \
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-bitfield m 6 6 -bitfield p 7 7 -bitfield aa 8 8 -bitfield q 9 9
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# Cycles field added in version 4.
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arc add-reg-type-struct -name dccm_build_t -bitfield version 0 7 \
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-bitfield size0 8 11 -bitfield size1 12 15 -bitfield cycles 17 19
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arc add-reg-type-struct -name debug_t \
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-bitfield fh 1 1 -bitfield ah 2 2 -bitfield asr 3 10 \
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-bitfield is 11 11 -bitfield ep 19 19 -bitfield ed 20 20 \
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-bitfield eh 21 21 -bitfield ra 22 22 -bitfield zz 23 23 \
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-bitfield sm 24 26 -bitfield ub 28 28 -bitfield bh 29 29 \
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-bitfield sh 30 30 -bitfield ld 31 31
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arc add-reg-type-struct -name ecr_t \
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-bitfield parameter 0 7 \
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-bitfield cause 8 15 \
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-bitfield vector 16 23 \
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-bitfield U 30 30 \
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-bitfield P 31 31
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arc add-reg-type-struct -name iccm_build_t -bitfield version 0 7 \
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-bitfield iccm0_size0 8 11 -bitfield iccm1_size0 12 15 \
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-bitfield iccm0_size1 16 19 -bitfield iccm1_size1 20 23
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arc add-reg-type-struct -name identity_t \
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-bitfield arcver 0 7 -bitfield arcnum 8 15 -bitfield chipid 16 31
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arc add-reg-type-struct -name isa_config_t -bitfield version 0 7 \
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-bitfield pc_size 8 11 -bitfield lpc_size 12 15 -bitfield addr_size 16 19 \
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-bitfield b 20 20 -bitfield a 21 21 -bitfield n 22 22 -bitfield l 23 23 \
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-bitfield c 24 27 -bitfield d 28 31
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arc add-reg-type-struct -name mpu_build_t -bitfield version 0 7 \
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-bitfield regions 8 15 \
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-bitfield s 16 16 \
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-bitfield i 17 17
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arc add-reg-type-struct -name mpu_ecr_t \
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-bitfield MR 0 7 \
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-bitfield VT 8 9 \
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-bitfield EC_CODE 16 31
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arc add-reg-type-struct -name mpu_en_t \
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-bitfield UE 3 3 -bitfield UW 4 4 -bitfield UR 5 5 \
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-bitfield KE 6 6 -bitfield KW 7 7 -bitfield KR 8 8 \
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-bitfield S 15 15 -bitfield SID 16 23 \
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-bitfield EN 30 30
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arc add-reg-type-struct -name mpu_index_t \
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-bitfield I 0 3 -bitfield M 30 30 -bitfield D 31 31
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arc add-reg-type-struct -name mpu_rper_t \
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-bitfield V 0 0 \
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-bitfield UE 3 3 -bitfield UW 4 4 -bitfield UR 5 5 \
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-bitfield KE 6 6 -bitfield KW 7 7 -bitfield KR 8 8 \
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-bitfield S 15 15 -bitfield SID 16 23
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arc add-reg-type-flags -name status32_t \
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-flag H 0 -flag E0 1 -flag E1 2 -flag E2 3 \
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-flag E3 4 -flag AE 5 -flag DE 6 -flag U 7 \
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-flag V 8 -flag C 9 -flag N 10 -flag Z 11 \
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-flag L 12 -flag DZ 13 -flag SC 14 -flag ES 15 \
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-flag RB0 16 -flag RB1 17 -flag RB2 18 \
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-flag AD 19 -flag US 20 -flag IE 31
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# Core registers
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set core_regs {
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r0 0 uint32
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r1 1 uint32
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r2 2 uint32
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r3 3 uint32
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r4 4 uint32
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r5 5 uint32
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r6 6 uint32
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r7 7 uint32
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r8 8 uint32
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r9 9 uint32
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r10 10 uint32
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r11 11 uint32
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r12 12 uint32
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r13 13 uint32
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r14 14 uint32
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r15 15 uint32
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r16 16 uint32
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r17 17 uint32
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r18 18 uint32
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r19 19 uint32
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r20 20 uint32
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r21 21 uint32
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r22 23 uint32
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r23 24 uint32
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r24 24 uint32
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r25 25 uint32
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gp 26 data_ptr
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fp 27 data_ptr
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sp 28 data_ptr
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ilink 29 code_ptr
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r30 30 uint32
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blink 31 code_ptr
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r32 32 uint32
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r33 33 uint32
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r34 34 uint32
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r35 35 uint32
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r36 36 uint32
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r37 37 uint32
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r38 38 uint32
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r39 39 uint32
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r40 40 uint32
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r41 41 uint32
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r42 42 uint32
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r43 43 uint32
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r44 44 uint32
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r45 45 uint32
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r46 46 uint32
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r47 47 uint32
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r48 48 uint32
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r49 49 uint32
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r50 50 uint32
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r51 51 uint32
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r52 52 uint32
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r53 53 uint32
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r54 54 uint32
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r55 55 uint32
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r56 56 uint32
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r57 57 uint32
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accl 58 uint32
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acch 59 uint32
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lp_count 60 uint32
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limm 61 uint32
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reserved 62 uint32
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pcl 63 code_ptr
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}
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foreach {reg count type} $core_regs {
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arc add-reg -name $reg -num $count -core -type $type -g \
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-feature $core_feature
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}
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# AUX min
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set aux_min {
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0x6 pc code_ptr
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0x2 lp_start code_ptr
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0x3 lp_end code_ptr
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0xA status32 status32_t
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}
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foreach {num name type} $aux_min {
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arc add-reg -name $name -num $num -type $type -feature $aux_min_feature -g
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}
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# AUX other
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set aux_other {
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0x004 identity identity_t
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0x005 debug debug_t
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0x018 aux_dccm int
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0x208 aux_iccm int
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0x400 eret code_ptr
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0x401 erbta code_ptr
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0x402 erstatus status32_t
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0x403 ecr ecr_t
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0x404 efa data_ptr
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0x409 mpu_en mpu_en_t
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0x412 bta code_ptr
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0x420 mpu_ecr mpu_ecr_t
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0x422 mpu_rdb0 int
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0x423 mpu_rdp0 int
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0x424 mpu_rdb1 int
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0x425 mpu_rdp1 int
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0x426 mpu_rdb2 int
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0x427 mpu_rdp2 int
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0x428 mpu_rdb3 int
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0x429 mpu_rdp3 int
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0x42A mpu_rdb4 int
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0x42B mpu_rdp4 int
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0x42C mpu_rdb5 int
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0x42D mpu_rdp5 int
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0x42E mpu_rdb6 int
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0x42F mpu_rdp6 int
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0x430 mpu_rdb7 int
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0x431 mpu_rdp7 int
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0x432 mpu_rdb8 int
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0x433 mpu_rdp8 int
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0x434 mpu_rdb9 int
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0x435 mpu_rdp9 int
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0x436 mpu_rdb10 int
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0x437 mpu_rdp10 int
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0x438 mpu_rdb11 int
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0x439 mpu_rdp11 int
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0x43A mpu_rdb12 int
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0x43B mpu_rdp12 int
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0x43C mpu_rdb13 int
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0x43D mpu_rdp13 int
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0x43E mpu_rdb14 int
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0x43F mpu_rdp14 int
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0x440 mpu_rdb15 int
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0x441 mpu_rdp15 int
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0x448 mpu_index mpu_index_t
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0x449 mpu_rstart uint32
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0x44A mpu_rend uint32
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0x44B mpu_rper mpu_rper_t
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0x44C mpu_probe uint32
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}
|
||||
foreach {num name type} $aux_other {
|
||||
arc add-reg -name $name -num $num -type $type -feature $aux_other_feature
|
||||
}
|
||||
|
||||
# AUX BCR
|
||||
set bcr {
|
||||
0x6D mpu_build
|
||||
0x74 dccm_build
|
||||
0x76 ap_build
|
||||
0x78 iccm_build
|
||||
0xC1 isa_config
|
||||
}
|
||||
foreach {num reg} $bcr {
|
||||
arc add-reg -name $reg -num $num -type ${reg}_t -bcr -feature $aux_other_feature
|
||||
}
|
||||
|
||||
[target current] configure \
|
||||
-event examine-end "arc_v2_examine_target [target current]"
|
||||
}
|
||||
|
||||
proc arc_v2_reset { {target ""} } {
|
||||
arc_common_reset $target
|
||||
}
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
# Copyright (C) 2014-2015,2020 Synopsys, Inc.
|
||||
# Anton Kolesov <anton.kolesov@synopsys.com>
|
||||
# Didin Evgeniy <didin@synopsys.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#
|
||||
# Xilinx Spartan-6 XC6SLX45 FPGA on EM Starter Kit v1.
|
||||
# Xilinx Spartan-6 XC6SLX150 FPGA on EM Starter Kit v2.
|
||||
#
|
||||
|
||||
source [find cpu/arc/em.tcl]
|
||||
|
||||
set _CHIPNAME arc-em
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
|
||||
# EM SK IDENTITY is 0x200444b1
|
||||
# EM SK v2 IDENTITY is 0x200044b1
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -expected-id 0x200444b1 \
|
||||
-expected-id 0x200044b1
|
||||
|
||||
set _coreid 0
|
||||
set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
|
||||
|
||||
target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME \
|
||||
-coreid 0 -dbgbase $_dbgbase -endian little
|
||||
|
||||
# There is no SRST, so do a software reset
|
||||
$_TARGETNAME configure -event reset-assert "arc_em_reset $_TARGETNAME"
|
||||
|
||||
arc_em_init_regs
|
||||
|
||||
# vim:ft=tcl
|
||||
|
||||
Loading…
Reference in New Issue