Introduce tcl config files for Synopsys HSDK board
With this commit we add tcl configure files for ARCv2 HS Development kit(HSDK). HSDK board has Quad-core ARC HS38 CPU with L1 and L2 caches. Change-Id: I372ef45428c7c7ca1421a6da3e5ed08b86f705e0 Signed-off-by: Evgeniy Didin <didin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5784 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Evgeniy Didin
Antonio Borneo
parent
8fea8460db
commit
b2821b6074
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# Copyright (C) 2019, 2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Synopsys DesignWare ARC HSDK Software Development Platform (HS38 cores)
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#
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source [find interface/ftdi/snps_sdp.cfg]
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adapter_khz 10000
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# ARCs supports only JTAG.
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transport select jtag
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# Configure SoC
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source [find target/snps_hsdk.cfg]
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# Copyright (C) 2015, 2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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source [find cpu/arc/v2.tcl]
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proc arc_hs_examine_target { target } {
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# Will set current target for us.
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arc_v2_examine_target $target
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}
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proc arc_hs_init_regs { } {
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arc_v2_init_regs
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[target current] configure \
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-event examine-end "arc_hs_examine_target [target current]"
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}
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# Scripts in "target" folder should call this function instead of direct
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# invocation of arc_common_reset.
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proc arc_hs_reset { {target ""} } {
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arc_v2_reset $target
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# Invalidate L2 cache if there is one.
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set l2_config [$target arc jtag get-aux-reg 0x901]
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# Will return 0, if cache is not present and register doesn't exist.
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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if { ($l2_config != 0) && (($l2_ctrl & 1) == 0) } {
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puts "L2 cache is present and not disabled"
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# Wait until BUSY bit is 0.
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puts "Invalidating L2 cache..."
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$target arc jtag set-aux-reg 0x905 1
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# Dummy read of SLC_AUX_CACHE_CTRL bit, as described in:
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# https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/commit/arch/arc?id=c70c473396cbdec1168a6eff60e13029c0916854
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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while { ($l2_ctrl & 0x100) != 0 } {
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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}
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# Flush cache if needed. If SLC_AUX_CACHE_CTRL.IM is 1, then invalidate
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# operation already flushed everything.
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if { ($l2_ctrl & 0x40) == 0 } {
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puts "Flushing L2 cache..."
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$target arc jtag set-aux-reg 0x904 1
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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while { [expr $l2_ctrl & 0x100] != 0 } {
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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}
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}
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puts "L2 cache has been flushed and invalidated."
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}
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}
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# Copyright (C) 2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Synopsys SDP Mainboard has embdded FT2232 chip, which is similiar to Digilent
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# HS-1, except that it uses channel B for JTAG communication, instead of
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# channel A.
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#
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adapter driver ftdi
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ftdi_vid_pid 0x0403 0x6010
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ftdi_layout_init 0x0088 0x008b
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ftdi_channel 1
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# Copyright (C) 2019,2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# HS Development Kit SoC.
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#
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# Contains quad-core ARC HS38.
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#
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source [find cpu/arc/hs.tcl]
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set _coreid 0
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set _dbgbase [expr ($_coreid << 13)]
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# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
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# OpenOCD is concerned EM and HS are identical.
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set _CHIPNAME arc-em
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# OpenOCD discovers JTAG TAPs in reverse order.
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# ARC HS38 core 4
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set _TARGETNAME $_CHIPNAME.cpu4
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jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1
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target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
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$_TARGETNAME configure -coreid $_coreid
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$_TARGETNAME configure -dbgbase $_dbgbase
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# Flush L2$.
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$_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME"
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set _coreid [expr $_coreid + 1]
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set _dbgbase [expr ($_coreid << 13)]
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arc_hs_init_regs
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# Enable L2 cache support for core 4.
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$_TARGETNAME arc cache l2 auto 1
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# ARC HS38 core 3
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set _TARGETNAME $_CHIPNAME.cpu3
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jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1
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target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
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$_TARGETNAME configure -coreid $_coreid
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$_TARGETNAME configure -dbgbase $_dbgbase
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$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
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set _coreid [expr $_coreid + 1]
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set _dbgbase [expr ($_coreid << 13)]
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arc_hs_init_regs
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# Enable L2 cache support for core 3.
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$_TARGETNAME arc cache l2 auto 1
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# ARC HS38 core 2
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set _TARGETNAME $_CHIPNAME.cpu2
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jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
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target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
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$_TARGETNAME configure -coreid $_coreid
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$_TARGETNAME configure -dbgbase $_dbgbase
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$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
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set _coreid [expr $_coreid + 1]
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set _dbgbase [expr ($_coreid << 13)]
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arc_hs_init_regs
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# Enable L2 cache support for core 2.
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$_TARGETNAME arc cache l2 auto 1
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# ARC HS38 core 1
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set _TARGETNAME $_CHIPNAME.cpu1
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jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1
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target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
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$_TARGETNAME configure -coreid $_coreid
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$_TARGETNAME configure -dbgbase $_dbgbase
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$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
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set _coreid [expr $_coreid + 1]
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set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
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arc_hs_init_regs
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# Enable L2 cache support for core 1.
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$_TARGETNAME arc cache l2 auto 1
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