stm32h7x.cfg: alignment with RM0399 rev3
in RM0399 rev2, there was these bits in DBGMCU_CR registers: - DBGSTBY_D3 : bit 7 - DBGSTOP_D3 : bit 8 these bits have been changed to reserved in rev3 Change-Id: I9d10d90e383795dc8e25a117d59fa065dc594610 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5861 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
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@ -149,8 +149,10 @@ $_CHIPNAME.cpu0 configure -event examine-end {
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stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
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# Enable debug during low power modes (uses more power)
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3, D2 & D1 Domains
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stm32h7x_dbgmcu_mmw 0x004 0x000001BF 0
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D1 Domain
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stm32h7x_dbgmcu_mmw 0x004 0x00000007 0
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D2 Domain
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stm32h7x_dbgmcu_mmw 0x004 0x00000038 0
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# Stop watchdog counters during halt
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# DBGMCU_APB3FZ1 |= WWDG1
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