| .. |
|
dynamic_part_select
|
Modifications of tests as per Eddie's request
|
2020-04-20 12:45:35 -05:00 |
|
.gitignore
|
tests: add a quick plugin test
|
2020-04-09 09:45:20 -07:00 |
|
abc9.v
|
Another sloppy mistake!
|
2019-11-21 16:33:20 -08:00 |
|
abc9.ys
|
abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_
|
2020-05-29 17:17:40 -07:00 |
|
async.sh
|
…
|
|
|
async.v
|
…
|
|
|
attrib05_port_conn.v
|
…
|
|
|
attrib05_port_conn.ys
|
…
|
|
|
attrib07_func_call.v
|
tests: fix some test warnings
|
2020-05-25 10:07:58 -07:00 |
|
attrib07_func_call.ys
|
…
|
|
|
autoname.ys
|
autoname: add testcase with $-prefix-ed port
|
2020-01-14 10:13:03 -08:00 |
|
bug1496.ys
|
Fix #1496.
|
2019-11-18 04:16:48 +01:00 |
|
bug1531.ys
|
Add testcase
|
2019-12-11 16:52:37 -08:00 |
|
bug1614.ys
|
add testcase for #1614
|
2020-02-03 21:29:54 +01:00 |
|
bug1710.ys
|
ast: fixes #1710; do not generate RTLIL for unreachable ternary
|
2020-02-27 16:55:55 -08:00 |
|
bug1745.ys
|
Add regression tests for new handling of comments in constants
|
2020-03-14 11:41:09 +01:00 |
|
bug1781.ys
|
fsm_extract: Initialize celltypes with full design.
|
2020-03-19 18:51:21 +01:00 |
|
bug1876.ys
|
tests: add testcases from #1876
|
2020-04-14 12:39:10 -07:00 |
|
bug2014.ys
|
test: add test for #2014
|
2020-05-02 14:22:37 -07:00 |
|
chparam.sh
|
…
|
|
|
const_func.v
|
Allow constant function calls in for loops and generate if and case
|
2020-06-29 16:06:17 -06:00 |
|
const_func.ys
|
Allow constant function calls in for loops and generate if and case
|
2020-06-29 16:06:17 -06:00 |
|
constcomment.ys
|
Add regression tests for new handling of comments in constants
|
2020-03-14 11:41:09 +01:00 |
|
constmsk_test.v
|
…
|
|
|
constmsk_test.ys
|
…
|
|
|
constmsk_testmap.v
|
tests: fix some test warnings
|
2020-05-25 10:07:58 -07:00 |
|
deminout_unused.ys
|
deminout: Don't demote inouts with unused bits
|
2020-03-04 18:44:38 +00:00 |
|
design.ys
|
design: add test
|
2020-04-16 12:48:40 -07:00 |
|
design1.ys
|
design: add test
|
2020-04-16 12:48:40 -07:00 |
|
design2.ys
|
tests: add design -delete tests
|
2020-04-16 08:05:18 -07:00 |
|
dynamic_part_select.ys
|
Remove '-ignore_unknown_cells' option from 'sat'
|
2020-04-20 11:58:23 -07:00 |
|
elab_sys_tasks.sv
|
…
|
|
|
elab_sys_tasks.ys
|
…
|
|
|
equiv_opt_multiclock.ys
|
…
|
|
|
exec.ys
|
Add test for `exec` command.
|
2020-03-16 07:52:58 +00:00 |
|
gen_if_null.v
|
verilog: allow null gen-if then block
|
2020-05-06 08:43:02 -04:00 |
|
gen_if_null.ys
|
verilog: allow null gen-if then block
|
2020-05-06 08:43:02 -04:00 |
|
global_scope.ys
|
ast: Fix handling of identifiers in the global scope
|
2020-04-16 10:30:07 +01:00 |
|
gzip_verilog.v.gz
|
…
|
|
|
gzip_verilog.ys
|
…
|
|
|
help.ys
|
Add "help -all" and "help -celltypes" sanity test
|
2020-01-28 18:11:34 -08:00 |
|
hierarchy.sh
|
…
|
|
|
hierarchy_defer.ys
|
…
|
|
|
hierarchy_param.ys
|
hierarchy: Convert positional parameters to named.
|
2020-04-21 19:09:00 +02:00 |
|
ice40_mince_abc9.ys
|
Add test for abc9+mince issue
|
2020-03-20 20:35:28 +00:00 |
|
integer_range_bad_syntax.ys
|
Revert "Revert PRs #2203 and #2244."
|
2020-07-10 09:59:48 +02:00 |
|
integer_real_bad_syntax.ys
|
Revert "Revert PRs #2203 and #2244."
|
2020-07-10 09:59:48 +02:00 |
|
logger_error.ys
|
Added back tests for logger
|
2020-03-13 15:00:18 +01:00 |
|
logger_nowarning.ys
|
Added back tests for logger
|
2020-03-13 15:00:18 +01:00 |
|
logger_warn.ys
|
Added back tests for logger
|
2020-03-13 15:00:18 +01:00 |
|
logger_warning.ys
|
Added back tests for logger
|
2020-03-13 15:00:18 +01:00 |
|
logic_param_simple.ys
|
Revert "Revert PRs #2203 and #2244."
|
2020-07-10 09:59:48 +02:00 |
|
mem2reg.ys
|
Change attribute search value to specify precise location instead of simple line number.
|
2020-02-24 01:39:36 +00:00 |
|
muxcover.ys
|
…
|
|
|
muxpack.v
|
…
|
|
|
muxpack.ys
|
…
|
|
|
peepopt.ys
|
…
|
|
|
plugin.cc
|
Use C++11 final/override keywords.
|
2020-06-18 23:34:52 +00:00 |
|
plugin.sh
|
tests: use `yosys-config --datdir` instead of hard-coded
|
2020-04-22 08:29:45 -07:00 |
|
pmgen_reduce.ys
|
…
|
|
|
pmux2shiftx.v
|
Cleanup tests
|
2020-02-27 10:17:29 -08:00 |
|
pmux2shiftx.ys
|
…
|
|
|
primitives.ys
|
tests: add tests for primitives' src
|
2020-05-04 10:21:47 -07:00 |
|
printattr.ys
|
printattrs: Add test.
|
2020-05-27 08:00:00 +00:00 |
|
reg_wire_error.sv
|
…
|
|
|
reg_wire_error.ys
|
…
|
|
|
run-test.sh
|
…
|
|
|
scratchpad.ys
|
add assert option to scratchpad command
|
2019-12-16 14:00:21 +01:00 |
|
script.ys
|
…
|
|
|
sformatf.ys
|
ast: Add support for $sformatf system function
|
2020-01-19 21:20:17 +00:00 |
|
shregmap.v
|
tests: fix some test warnings
|
2020-05-25 10:07:58 -07:00 |
|
shregmap.ys
|
…
|
|
|
signed.ys
|
Revert "Revert PRs #2203 and #2244."
|
2020-07-10 09:59:48 +02:00 |
|
signext.ys
|
…
|
|
|
sim_const.ys
|
sim: Fix handling of constant-connected cell inputs at startup
|
2020-04-21 08:58:52 +01:00 |
|
specify.v
|
verilog: ignore ranges too without -specify
|
2020-02-13 17:58:43 -08:00 |
|
specify.ys
|
verilog: fix specify src attribute
|
2020-05-04 10:53:06 -07:00 |
|
src.ys
|
verilog: add test
|
2020-03-11 06:51:03 -07:00 |
|
submod.ys
|
Remove submod changes
|
2019-12-30 14:56:14 -08:00 |
|
submod_extract.ys
|
…
|
|
|
sv_defines.ys
|
Add support for SystemVerilog-style `define to Verilog frontend
|
2020-03-27 16:08:26 +00:00 |
|
sv_defines_dup.ys
|
Add support for SystemVerilog-style `define to Verilog frontend
|
2020-03-27 16:08:26 +00:00 |
|
sv_defines_mismatch.ys
|
Add support for SystemVerilog-style `define to Verilog frontend
|
2020-03-27 16:08:26 +00:00 |
|
sv_defines_too_few.ys
|
Add support for SystemVerilog-style `define to Verilog frontend
|
2020-03-27 16:08:26 +00:00 |
|
sv_implicit_ports.sh
|
sv: More tests for wildcard port connections
|
2020-02-02 16:12:33 +00:00 |
|
svalways.sh
|
sv: Add tests for SV always types
|
2019-11-21 21:06:28 +00:00 |
|
wreduce.ys
|
…
|
|
|
write_gzip.ys
|
…
|
|
|
xaiger.ys
|
xaiger: add testcase
|
2020-05-24 08:48:23 -07:00 |
de649b9194