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11367 Commits

Author SHA1 Message Date
Miodrag Milanovic cb17eeaf50 Update manual 2022-01-03 11:57:11 +01:00
github-actions[bot] cfe940a98b Bump version 2021-12-26 01:00:33 +00:00
Catherine ebe396a2ab
Merge pull request #3127 from whitequark/cxxrtl-no-reset-elided 
cxxrtl: don't reset elided wires with \init attribute
 2021-12-25 12:29:44 +00:00
Catherine fc049e84a9 cxxrtl: don't reset elided wires with \init attribute. 2021-12-25 01:06:10 +00:00
github-actions[bot] 7407a7f3ef Bump version 2021-12-22 00:58:25 +00:00
Lofty d015c2b48a intel_alm: disable 256x40 M10K mode 
This BRAM mode uses both address ports, making it effectively single-port.
Since memory_bram can't presently map to single-port memories, remove it.
 2021-12-22 00:42:33 +01:00
github-actions[bot] 229980d663 Bump version 2021-12-21 00:59:45 +00:00
Marcelina Kościelnicka f84c9d8e17 memory_share: Fix SAT-based sharing for wide ports. 
Fixes #3117.
 2021-12-20 18:40:14 +01:00
github-actions[bot] f599c148c5 Bump version 2021-12-19 01:00:40 +00:00
Zachary Snow 7608985d2c fix width detection of array querying function in case and case item expressions 
I also removed the unnecessary shadowing of `width_hint` and `sign_hint`
in the corresponding case in `simplify()`.
 2021-12-17 21:22:08 -07:00
Icenowy Zheng c2b7ad3b28 anlogic: support BRAM mapping 
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.

Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2021-12-17 20:28:22 +08:00
github-actions[bot] 60c3ea367c Bump version 2021-12-17 00:58:02 +00:00
Catherine ed4642e18e
Merge pull request #3115 from whitequark/issue-3112 
cxxrtl: demote wires not inlinable only in debug_eval to locals
 2021-12-16 07:29:29 +00:00
Catherine 73eea51613
Merge pull request #3114 from whitequark/issue-3113 
bugpoint: avoid infinite loop between -connections and -wires
 2021-12-16 07:29:19 +00:00
Thomas Sailer 4cd2f03e36 preprocessor: do not destroy double slash escaped identifiers 
The preprocessor currently destroys double slash containing escaped
identifiers (for example \a//b ). This is due to next_token trying to
convert single line comments (//) into /* */ comments. This then leads
to an unintuitive error message like this:
ERROR: syntax error, unexpected '*'

This patch fixes the error by recognizing escaped identifiers and
returning them as single token. It also adds a testcase.
 2021-12-15 18:06:02 -07:00
Catherine 7f2ea7d222 cxxrtl: demote wires not inlinable only in debug_eval to locals. 
Fixes #3112.

Co-authored-by: Irides <irides@irides.network>
 2021-12-15 09:14:33 +00:00
Catherine 4f1d62d9b2 bugpoint: avoid infinite loop between -connections and -wires. 
Fixes #3113.
 2021-12-15 08:17:02 +00:00
github-actions[bot] 477eeefd9b Bump version 2021-12-15 00:59:04 +00:00
Catherine 5dadcc85b7
Merge pull request #3111 from whitequark/issue-3110 
Fix null pointer dereference after failing to extract DFF from memory
 2021-12-14 21:25:06 +00:00
Claire Xenia Wolf e1c7a9a647 Hotfix for run_shell auto-detection 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-14 21:38:58 +01:00
Catherine 48ed6d998b Fix null pointer dereference after failing to extract DFF from memory. 
Fixes #3110.
 2021-12-14 16:27:37 +00:00
github-actions[bot] b07ca8756a Bump version 2021-12-14 00:59:10 +00:00
Claire Xen 5e5c8a54ce
Merge pull request #3108 from YosysHQ/claire/verificdefs 
Add YOSYS to the implicitly defined verilog macros in verific
 2021-12-13 22:03:29 +01:00
Claire Xenia Wolf 313340aed5 Add YOSYS to the implicitly defined verilog macros in verific 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-13 18:20:08 +01:00
github-actions[bot] 19a38222e7 Bump version 2021-12-13 00:55:45 +00:00
Marcelina Kościelnicka 0aad88a2fb Add clean_zerowidth pass, use it for Verilog output. 
This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.
 2021-12-12 19:56:50 +01:00
Catherine bdc6ba019c
Merge pull request #3105 from whitequark/cxxrtl-reset-memories-2 
cxxrtl: preserve interior memory pointers across reset
 2021-12-12 01:23:03 +00:00
github-actions[bot] 6a7253b46e Bump version 2021-12-12 01:12:53 +00:00
Marcelina Kościelnicka 26f0f6bb0b Fix unused param warning with ENABLE_NDEBUG. 2021-12-12 01:22:28 +01:00
Marcelina Kościelnicka d019b4e681 rtlil: Dump empty connections when whole module is selected. 
Without this, empty connections will be always skipped by `dump`, since
they contain no selected wires.  This makes debugging rather confusing.
 2021-12-12 01:22:06 +01:00
Catherine 55c9fb3b18 cxxrtl: preserve interior memory pointers across reset. 
Before this commit, values, wires, and memories with an initializer
were value-initialized in emitted C++ code. After this commit, all
values, wires, and memories are default-initialized, and the default
constructor of generated modules calls the reset() method, which
assigns the members that have an initializer.
 2021-12-11 16:40:06 +00:00
Catherine 21fbdb6638
Merge pull request #3103 from whitequark/write_verilog-more-zero-width-values 
write_verilog: dump zero width sigspecs correctly
 2021-12-11 16:24:47 +00:00
whitequark 7c9e498662 cxxrtl: use unique_ptr<value<>[]> to store memory contents. 
This makes the depth properly immutable.
 2021-12-11 14:52:37 +00:00
whitequark 86f2804dc3 write_verilog: dump zero width sigspecs correctly. 
Before this commit, zero width sigspecs were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.

After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)

PR #1203 has addressed this issue before, but in an incomplete way.
 2021-12-11 12:01:52 +00:00
github-actions[bot] 8e91857fab Bump version 2021-12-11 00:54:59 +00:00
Miodrag Milanović 2412497c26
Merge pull request #3102 from YosysHQ/claire/enumxz 
Fix verific import of enum values with x and/or z
 2021-12-10 19:36:37 +01:00
Claire Xenia Wolf 2da214d721 Fix verific import of enum values with x and/or z 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-10 14:52:27 +01:00
Miodrag Milanović f8978f9e0a
Merge pull request #3097 from YosysHQ/modport 
If direction NONE use that from first bit
 2021-12-10 14:32:14 +01:00
Claire Xen 19773d093f
Update verific.cc 
Ad-hoc fixes/improvements
 2021-12-10 14:27:18 +01:00
Claire Xen ce82afe44f
Merge pull request #3099 from YosysHQ/claire/readargs 
Use "read" command to parse HDL files from Yosys command-line
 2021-12-10 11:23:53 +01:00
Claire Xenia Wolf d6e4d3f1ba Fix the tests we just broke 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-10 00:22:37 +01:00
Claire Xenia Wolf ce08046f44 Added "yosys -r <topmodule>" 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-10 00:15:37 +01:00
Claire Xenia Wolf 0cbdb42dcd Use "read" command to parse HDL files from Yosys command-line 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-09 10:33:55 +01:00
github-actions[bot] cdb5711875 Bump version 2021-12-09 00:55:26 +00:00
Marcelina Kościelnicka 1184a7f3b4 opt_mem_priority: Fix non-ascii char in help message. 
This is a fixed version of #3072.
 2021-12-09 00:56:14 +01:00
Miodrag Milanovic b06f547993 If direction NONE use that from first bit 2021-12-08 11:50:10 +01:00
github-actions[bot] d186ea7a2d Bump version 2021-12-04 00:54:12 +00:00
Miodrag Milanovic c23cd00f30 Next dev cycle 2021-12-03 12:51:34 +01:00
Miodrag Milanovic 2156e20db5 Release version 0.12 2021-12-03 12:48:49 +01:00
Miodrag Milanovic 71e762d68c Update manual 2021-12-03 09:57:14 +01:00