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Merge pull request #3097 from YosysHQ/modport 

If direction NONE use that from first bit
This commit is contained in:
Miodrag Milanović 2021-12-10 14:32:14 +01:00 committed by GitHub
parent ce82afe44f 19773d093f
commit f8978f9e0a
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1 changed files with 12 additions and 2 deletions
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14
frontends/verific/verific.cc
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@ -1105,18 +1105,28 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex());
import_attributes(wire->attributes, portbus, nl);
if (portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN)
bool portbus_input = portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN;
if (portbus_input)
wire->port_input = true;
if (portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_OUT)
wire->port_output = true;
for (int i = portbus->LeftIndex();; i += portbus->IsUp() ? +1 : -1) {
if (portbus->ElementAtIndex(i) && portbus->ElementAtIndex(i)->GetNet()) {
bool bit_input = portbus_input;
if (portbus->GetDir() == DIR_NONE) {
Port *p = portbus->ElementAtIndex(i);
bit_input = p->GetDir() == DIR_INOUT || p->GetDir() == DIR_IN;
if (bit_input)
wire->port_input = true;
if (p->GetDir() == DIR_INOUT || p->GetDir() == DIR_OUT)
wire->port_output = true;
}
net = portbus->ElementAtIndex(i)->GetNet();
RTLIL::SigBit bit(wire, i - wire->start_offset);
if (net_map.count(net) == 0)
net_map[net] = bit;
else if (wire->port_input)
else if (bit_input)
module->connect(net_map_at(net), bit);
else
module->connect(bit, net_map_at(net));