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cxxrtl: don't reset elided wires with \init attribute.
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@ -1838,6 +1838,8 @@ struct CxxrtlWorker {
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int mem_init_idx = 0;
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inc_indent();
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for (auto wire : module->wires()) {
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const auto &wire_type = wire_types[wire];
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if (!wire_type.is_named() || wire_type.is_local()) continue;
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if (!wire_init.count(wire)) continue;
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f << indent << mangle(wire) << " = ";
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