Eddie Hung
bfd71e0990
Fix abc9 with (* keep *) wires
2019-04-23 16:11:14 -07:00
Eddie Hung
4883391b63
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 11:19:52 -07:00
Clifford Wolf
a80e74dc20
Updaye pmux2shiftx test
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 16:17:43 +02:00
Clifford Wolf
b40af877f3
Merge pull request #909 from zachjs/master
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support repeat loops with constant repeat counts outside of constant functions
2019-04-22 08:51:34 +02:00
Clifford Wolf
a98b171814
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx
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Add pmux2shiftx command
2019-04-22 08:39:37 +02:00
Eddie Hung
42a6e0b0b9
Merge remote-tracking branch 'origin/clifford/libwb' into xaig
2019-04-21 14:49:18 -07:00
Clifford Wolf
d38f0c1a96
Fix tests
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-21 11:40:20 +02:00
Eddie Hung
caec7f9d2c
Merge remote-tracking branch 'origin/master' into xaig
2019-04-20 12:23:49 -07:00
Clifford Wolf
b3a3e08e38
Improve "pmux2shiftx"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 02:03:44 +02:00
Clifford Wolf
37728520a6
Improvements in "pmux2shiftx"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 01:15:48 +02:00
Eddie Hung
59c993e437
Select to find union of both sets on stack
2019-04-19 15:47:53 -07:00
Clifford Wolf
0070184ea9
Improvements in pmux2shiftx
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 00:38:25 +02:00
Clifford Wolf
4c831d72ef
Add test for pmux2shiftx
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 00:38:25 +02:00
Clifford Wolf
ea2a21445e
Add tests/aiger/.gitignore
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-19 14:04:12 +02:00
Eddie Hung
0c8a839f13
Re-enable partsel.v test
2019-04-16 13:10:35 -07:00
Eddie Hung
0391499e46
Merge remote-tracking branch 'origin/master' into xaig
2019-04-15 21:56:45 -07:00
Eddie Hung
b3378745fd
Revert "Recognise default entry in case even if all cases covered (fix for #931 )"
2019-04-15 17:52:45 -07:00
Eddie Hung
f77da46a87
Merge remote-tracking branch 'origin/master' into xaig
2019-04-12 12:21:48 -07:00
Eddie Hung
7685469ee2
Add default entry to testcase
2019-04-11 15:03:40 -07:00
Zachary Snow
5855024ccc
support repeat loops with constant repeat counts outside of constant functions
2019-04-09 12:28:32 -04:00
Eddie Hung
bca3cf6843
Merge branch 'master' into xaig
2019-04-08 16:31:59 -07:00
Eddie Hung
ad602438b8
Add retime test
2019-04-05 16:28:46 -07:00
Niels Moseley
ee130f67cd
Liberty file parser now accepts superfluous ;
2019-03-27 15:16:19 +01:00
Niels Moseley
487cb45b87
Liberty file parser now accepts superfluous ;
2019-03-27 15:15:53 +01:00
Clifford Wolf
c863796e9f
Fix "verific -extnets" for more complex situations
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-26 14:17:46 +01:00
Niels Moseley
3b3b77291a
Updated the liberty parser to accept [A:B] ranges (AST has not been updated). Liberty parser now also accepts key : value pair lines that do not end in ';'.
2019-03-24 22:54:18 +01:00
Eddie Hung
02e8dc7ad2
Merge https://github.com/YosysHQ/yosys into read_aiger
2019-03-19 08:52:31 -07:00
Zachary Snow
a5f4b83637
fix local name resolution in prefix constructs
2019-03-18 20:43:20 -04:00
Clifford Wolf
a330c68363
Fix handling of task output ports in clocked always blocks, fixes #857
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 22:44:37 -08:00
Jim Lawson
d6c4dfb902
Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails
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Mark dff_init.v as expected to fail since it uses "initial value".
2019-03-04 13:37:23 -08:00
Clifford Wolf
b84febafd7
Hotfix for "make test"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 20:26:54 -08:00
Clifford Wolf
241901461a
Add "write_verilog -siminit"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 15:03:03 -08:00
Eddie Hung
f7c7003a19
Merge remote-tracking branch 'origin/master' into xaig
2019-02-26 13:16:03 -08:00
Eddie Hung
dfb23a79dd
Uncomment out more tests
2019-02-26 12:18:48 -08:00
Eddie Hung
66b5f5166b
Enable two inout tests
2019-02-26 11:39:17 -08:00
Jim Lawson
171c425cf9
Fix FIRRTL to Verilog process instance subfield assignment.
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Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
2019-02-25 16:18:13 -08:00
Eddie Hung
65c8ccf7b5
Add broken testcases
2019-02-25 15:06:23 -08:00
Clifford Wolf
c118f9a377
Merge pull request #812 from ucb-bar/arrayhierarchyfixes
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Define basic_cell_type() function and use it to derive the cell type …
2019-02-24 11:39:13 -08:00
Clifford Wolf
da14bc8524
Merge pull request #824 from litghost/fix_reduce_on_ff
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Fix WREDUCE on FF not fixing ARST_VALUE parameter.
2019-02-24 11:29:14 -08:00
Clifford Wolf
1816fe06af
Fix handling of defparam for when default_nettype is none
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:09:41 +01:00
Jim Lawson
71bcc4c644
Address requested changes - don't require non-$ name.
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Suppress warning if name does begin with a `$`.
Fix hierachy tests so they have something to grep.
Announce hierarchy test types.
2019-02-22 16:06:10 -08:00
Keith Rothman
25680f6a07
Fix WREDUCE on FF not fixing ARST_VALUE parameter.
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Adds test case that fails without code change.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-22 10:30:42 -08:00
Eddie Hung
ca870688c3
Revert "tests/simple to also do LUT synth"
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This reverts commit 5994382a20
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2019-02-21 13:15:45 -08:00
Eddie Hung
a8803a1519
Merge remote-tracking branch 'origin/master' into xaig
2019-02-21 11:23:00 -08:00
Eddie Hung
5994382a20
tests/simple to also do LUT synth
2019-02-21 11:16:57 -08:00
Eddie Hung
107da3becf
Working simple_abc9 tests
2019-02-21 11:16:25 -08:00
Eddie Hung
c6fd057eda
Add abc9.v testcase to simple_abc9
2019-02-21 10:37:45 -08:00
Eddie Hung
be061810d7
Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig
2019-02-21 09:31:17 -08:00
Eddie Hung
8e789da74c
Revert "Add -B option to autotest.sh to append to backend_opts"
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This reverts commit 281f2aadca
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2019-02-21 09:22:29 -08:00
Eddie Hung
869343b040
simple_abc9 tests to now preserve memories
2019-02-20 16:19:01 -08:00