riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
442 Commits 86 Branches 51 Tags 35 MiB
Commit Graph

119 Commits

Author SHA1 Message Date
Clifford Wolf 1dcb683fcb Write yosys version to output files 2013-11-03 21:41:39 +01:00
Clifford Wolf f39c0c9928 Fixed get_share_file_name() for installed yosys 2013-10-27 10:05:19 +01:00
Clifford Wolf 73e68fe323 Added API and Makefile rules for share/ files 2013-10-27 09:33:26 +01:00
Clifford Wolf bd2c8ec886 Added design->full_selection() helper method 2013-10-27 09:30:58 +01:00
Clifford Wolf e679a5d046 Fixed handling of boolean attributes (passes) 2013-10-24 11:37:54 +02:00
Clifford Wolf eae43e2db4 Fixed handling of boolean attributes (kernel) 2013-10-24 10:59:27 +02:00
Clifford Wolf 8e8f1994b8 Changed NEW_WIRE API to return the wire, not the signal 2013-10-18 14:19:45 +02:00
Clifford Wolf cc5e379eca Added RTLIL NEW_WIRE macro 2013-10-18 13:25:24 +02:00
Clifford Wolf e0f693cbb0 Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_ 2013-10-18 12:13:34 +02:00
Clifford Wolf 5998c101a4 Added $sr, $dffsr and $dlatch cell types 2013-10-18 11:56:16 +02:00
Clifford Wolf 485e870bcd Added version info to yosys command and added -V option 2013-08-20 09:48:12 +02:00
Clifford Wolf a860efa8ac Implemented same div-by-zero behavior as found in other synthesis tools 2013-08-15 21:00:06 +02:00
Clifford Wolf 78658199e6 Fixed signed div/mod in const eval (rounding and stuff) 2013-08-15 18:23:42 +02:00
Clifford Wolf 2f3da54f26 Added sat -ignore_div_by_zero switch 2013-08-15 11:40:01 +02:00
Clifford Wolf d0e93e04d1 Added eval -brute_force_equiv_checker_x mode 2013-08-15 11:09:30 +02:00
Clifford Wolf ccf36cb7d8 Added SAT support for $div and $mod cells 2013-08-11 16:27:15 +02:00
Clifford Wolf a5836af172 Added "clean -purge" and ";;;" support 2013-08-11 13:59:14 +02:00
Clifford Wolf 080f0aac34 Added ";;" as shortcut for "; clean;" 2013-08-11 13:33:38 +02:00
Clifford Wolf 376150c926 Added techmap -opt mode 2013-08-09 15:20:22 +02:00
Clifford Wolf 05483619f0 Some fixes to improve determinism 2013-08-09 12:42:32 +02:00
Clifford Wolf 117489f95a Fixed SigPool::del() method 2013-08-06 15:04:24 +02:00
Clifford Wolf ff965424c2 Added proper deallocation of history buffer 2013-08-06 15:03:46 +02:00
Clifford Wolf 0f38008ed3 Added "design" command (-reset, -save, -load) 2013-07-27 14:27:51 +02:00
Clifford Wolf 974b6a947c Added "help -write-web-command-reference-manual" 2013-07-26 00:01:31 +02:00
Clifford Wolf ad9bbcbf40 Added $lut cells and abc lut mapping support 2013-07-23 16:19:34 +02:00
Clifford Wolf 7daeee340a Fixed shift ops with large right hand side 2013-07-09 18:59:59 +02:00
Clifford Wolf 21e38bed98 Added "eval" pass 2013-06-19 09:30:37 +02:00
Clifford Wolf a046a302f0 Fixed build with clang 2013-06-18 19:54:33 +02:00
Clifford Wolf 6971c4db62 Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API 2013-06-18 17:11:13 +02:00
Clifford Wolf 6d7b5f9064 Fixed even more ConstEval bugs found using xsthammer 2013-06-14 17:50:26 +02:00
Clifford Wolf 30db70b1ba Added consteval testing to xsthammer and fixed bugs 2013-06-13 19:51:13 +02:00
Clifford Wolf 0c6ffc4c65 More fixes for bugs found using xsthammer 2013-06-13 11:18:45 +02:00
Clifford Wolf bf2c149329 Another fix for a bug found using xsthammer 2013-06-12 19:09:14 +02:00
Clifford Wolf a5c30183b5 Sign-extension related fixes in SatGen and AST frontend 2013-06-10 17:10:06 +02:00
Clifford Wolf 7d790febb0 Improvements and fixes in SAT code 2013-06-10 16:09:29 +02:00
Clifford Wolf 15ff4cc63b Added history file read/write to driver 2013-06-10 15:42:52 +02:00
Clifford Wolf a75b249427 Implemented temporal induction proofs in sat_solve 2013-06-09 18:07:05 +02:00
Clifford Wolf b7ba90910d Fixed handling of $_XOR_ in SAT generator 2013-06-09 14:01:50 +02:00
Clifford Wolf 0efde13775 Added sequential solving support to sat_solve 2013-06-09 13:35:46 +02:00
Clifford Wolf 6f330f0132 Set rl_basic_word_break_characters in shell 2013-06-09 11:51:06 +02:00
Clifford Wolf e52c9aff1b Improved readline tab completion 2013-06-09 01:04:23 +02:00
Clifford Wolf bf59a28f80 Look for yosys-abc and yosys-svgviewer where the main exe is 2013-06-09 00:07:26 +02:00
Clifford Wolf 5a592b3739 Moved cmds from kernel/ to passes/cmds/ 2013-06-08 23:16:36 +02:00
Clifford Wolf 23a7973094 Added support for shifter cells to SAT generator 2013-06-08 15:12:08 +02:00
Clifford Wolf 92f04eab10 Added "cd" and "ls" commands for convenience 2013-06-08 14:45:28 +02:00
Clifford Wolf 1434312fdd Various improvements in sat_solve pass and SAT generator 2013-06-08 14:11:50 +02:00
Clifford Wolf c681c17038 Improved auto-detection of -show signals in sat_solve 2013-06-08 09:34:36 +02:00
Clifford Wolf 56b593b91c Improved sat generator and sat_solve pass 2013-06-07 14:37:33 +02:00
Clifford Wolf 46fbe9d262 Added SAT generator and simple sat_solve command 2013-06-07 13:59:13 +02:00
Clifford Wolf 21d9251e52 Added "dump" command (part ilang backend) 2013-06-02 17:53:30 +02:00