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629 Commits 81 Branches 48 Tags 64 MiB
Commit Graph

119 Commits

Author SHA1 Message Date
Clifford Wolf 369bf81a70 Added support for non-const === and !== (for miter circuits) 2013-12-27 14:20:15 +01:00
Clifford Wolf ecc30255ba Added proper === and !== support in constant expressions 2013-12-27 13:50:08 +01:00
Clifford Wolf fbd06a1afc Added elsif preproc support 2013-12-18 13:41:36 +01:00
Clifford Wolf 921064c200 Added support for macro arguments 2013-12-18 13:21:02 +01:00
Clifford Wolf 891e4b5b0d Keep strings as strings in const ternary and concat 2013-12-05 13:26:17 +01:00
Clifford Wolf e935bb6eda Added const folding support for $signed and $unsigned 2013-12-05 13:09:41 +01:00
Clifford Wolf 5c39948ead Added AstNode::mkconst_str API 2013-12-05 12:53:49 +01:00
Clifford Wolf 853538d78b Fixed generate-for (and disabled double warning for auto-wire) 2013-12-04 21:33:00 +01:00
Clifford Wolf 3c220e0b32 Added support for $clog2 system function 2013-12-04 21:19:54 +01:00
Clifford Wolf 4a4a3fc337 Various improvements in support for generate statements 2013-12-04 21:06:54 +01:00
Clifford Wolf f4b46ed31e Replaced signed_parameters API with CONST_FLAG_SIGNED 2013-12-04 14:24:44 +01:00
Clifford Wolf 93a70959f3 Replaced RTLIL::Const::str with generic decoder method 2013-12-04 14:14:05 +01:00
Clifford Wolf 507c63d112 Added support for local regs in named blocks 2013-12-04 09:10:16 +01:00
Clifford Wolf 10aa08dca1 Fixed temp net name generation in rtlil process generator for abbreviated name matching 2013-11-28 21:47:08 +01:00
Clifford Wolf 0e52f3fa01 Added "src" attribute to processes 2013-11-28 17:37:50 +01:00
Clifford Wolf 8dafecd34d Added module->avail_parameters (for advanced techmap features) 2013-11-24 20:29:07 +01:00
Clifford Wolf 7d9a90396d Added verilog frontend -ignore_redef option 2013-11-24 19:57:42 +01:00
Clifford Wolf 019b301541 Early wire/reg/parameter width calculation in ast/simplify 2013-11-24 19:40:23 +01:00
Clifford Wolf 0ef22c7609 Added support for signed parameters in ilang 2013-11-24 17:37:27 +01:00
Clifford Wolf f71e27dbf1 Remove auto_wire framework (smarter than the verilog standard) 2013-11-24 17:29:11 +01:00
Clifford Wolf 609caa23b5 Implemented correct handling of signed module parameters 2013-11-24 17:17:21 +01:00
Clifford Wolf 1de12e1efc Improved handling of initialized registers 2013-11-23 16:26:59 +01:00
Clifford Wolf 295e352ba6 Renamed "placeholder" to "blackbox" 2013-11-22 15:01:12 +01:00
Clifford Wolf a362fd81ae Fixed O(n^2) performance bug in verilog preprocessor 2013-11-22 14:08:43 +01:00
Clifford Wolf e4429c480e Enable {* .. *} feature per default (removes dependency to REJECT feature in flex) 2013-11-22 12:46:02 +01:00
Clifford Wolf 95c94a02fc Fixed async proc detection in mem2reg 2013-11-21 21:26:56 +01:00
Clifford Wolf 09471846c5 Major improvements in mem2reg and added "init" sync rules 2013-11-21 13:49:00 +01:00
Clifford Wolf 08ceb3729e Fixed ilang parser: memory width 2013-11-20 19:55:52 +01:00
Clifford Wolf 65ad556f3d Another name resolution bugfix for generate blocks 2013-11-20 13:57:40 +01:00
Clifford Wolf 92035fb38e Implemented indexed part selects 2013-11-20 13:05:27 +01:00
Clifford Wolf c4c299eb5a Do not allow memory bit select on the left side of an assignment 2013-11-20 12:18:46 +01:00
Clifford Wolf 0f04738f40 Added "synthesis" in (synopsys|synthesis) comment support 2013-11-20 11:44:09 +01:00
Clifford Wolf ac2be2d892 Fixed name resolution of local tasks and functions in generate block 2013-11-20 11:05:58 +01:00
Clifford Wolf 19dba2561e Implemented part/bit select on memory read 2013-11-20 10:51:32 +01:00
Clifford Wolf e340532ce5 Added init= attribute for fpga-style reset values 2013-11-20 01:49:37 +01:00
Clifford Wolf 0dfdbd991a Fixed parsing of module arguments when one type is used for many args 2013-11-19 20:35:31 +01:00
Clifford Wolf 4f2edcf2f9 Fixed two bugs in mem2reg functionality in AST frontend 2013-11-18 19:55:12 +01:00
Clifford Wolf 79910a5547 Added dumping of attributes in AST frontend 2013-11-18 19:54:36 +01:00
Clifford Wolf 2a25e3bca3 Fixed parsing of default cases when not last case 2013-11-18 16:10:50 +01:00
Clifford Wolf de03184150 Fixed mem2reg for reg usage outside always block 2013-11-18 12:35:41 +01:00
Clifford Wolf 63060dcd2e Fixed parsing of "parameter integer" 2013-11-13 15:30:23 +01:00
Clifford Wolf e5b974fa2a Cleanups and bugfixes in response to new internal cell checker 2013-11-11 00:39:45 +01:00
Clifford Wolf 378cc509cd Call internal checker more often 2013-11-10 23:24:21 +01:00
Clifford Wolf 259cc1391e More undef-propagation related fixes 2013-11-08 11:40:36 +01:00
Clifford Wolf 9f49d538e1 Fixed handling of different signedness in power operands 2013-11-08 11:06:11 +01:00
Clifford Wolf 4abc8e695a Implemented const folding of ternary op with undef select 2013-11-08 04:44:09 +01:00
Clifford Wolf fc6dc0d7b8 Fixed handling of power operator 2013-11-07 22:20:00 +01:00
Clifford Wolf d7cb62ac96 Fixed more extend vs. extend_u0 issues 2013-11-07 19:20:20 +01:00
Clifford Wolf 02f4f89fdb Disabled const folding of ternary op when select is undef 2013-11-07 18:18:16 +01:00
Clifford Wolf 947bd9b96b Renamed extend_un0() to extend_u0() and use it in genrtlil 2013-11-07 18:17:10 +01:00