Emil J. Tywoniak
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898d042604
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hashlib: redo interface for flexibility
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2024-11-26 10:52:07 +01:00 |
Miodrag Milanović
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29e8812bab
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Merge pull request #4724 from YosysHQ/micko/blackbox_verific
verific: fix blackbox regression and add test case
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2024-11-25 15:06:54 +01:00 |
Miodrag Milanovic
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d6bd521487
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verific : VHDL assert DFF initial value set on Verific library patch side
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2024-11-21 13:43:26 +01:00 |
Martin Povišer
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1cb5fd08b7
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Merge pull request #4682 from povik/read_liberty-extensions
read_liberty extensions
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2024-11-18 14:42:18 +01:00 |
Mike Inouye
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06e3ac4415
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Fix bug when setting Verific runtime string flags.
Signed-off-by: Mike Inouye <mikeinouye@google.com>
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2024-11-12 18:46:26 +00:00 |
Martin Povišer
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0d5c412807
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read_liberty: s/busses/buses/
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2024-11-12 13:33:41 +01:00 |
Martin Povišer
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28aa7b00ee
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read_liberty: Start an `-ignore_busses` option
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2024-11-12 13:26:38 +01:00 |
Martin Povišer
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0e96e477a2
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read_liberty: Defer handling of re-definitions
Postpone handling re-definitions to after we have established the cell
is not supposed to be ignored on the grounds of one of the user-provided
flags.
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2024-11-12 13:26:38 +01:00 |
Martin Povišer
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c7e8d41600
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read_liberty: Set `area` `capacitance` attributes
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2024-11-12 13:26:38 +01:00 |
Miodrag Milanovic
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df391f5816
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verific: fix blackbox regression and add test case
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2024-11-08 14:57:04 +01:00 |
Krystine Sherwin
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ee73a91f44
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Remove references to ilang
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2024-11-05 12:36:31 +13:00 |
George Rennie
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dbfca1bdff
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frontends/ast.cc: special-case zero width strings as "\0"
* Fixes #4696
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2024-11-01 17:19:28 +01:00 |
Emil J. Tywoniak
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81bbde62ca
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verilog_parser: silence yynerrs warning
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2024-10-15 08:32:55 -04:00 |
Emil J
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caf56ca3e8
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Merge pull request #4516 from YosysHQ/emil/src-attribute-std-string-wip
Represent string constants as strings
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2024-10-14 06:42:54 -07:00 |
Emil J. Tywoniak
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785bd44da7
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rtlil: represent Const strings as std::string
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2024-10-14 06:28:12 +02:00 |
Miodrag Milanovic
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8d2b63bb8a
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Set VHDL assert condition initial state if fed by FF
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2024-10-11 16:32:21 +02:00 |
Martin Povišer
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0aab8b4158
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Merge pull request #4605 from povik/liberty-unit-delay
read_liberty: Optionally import unit delay arcs
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2024-10-07 16:11:51 +02:00 |
Martin Povišer
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74e92d10e8
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Merge pull request #4593 from povik/aiger2
New aiger backend
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2024-10-07 16:11:25 +02:00 |
Martin Povišer
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7989d53c58
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read_xaiger2: Add help
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2024-10-07 14:19:49 +02:00 |
Martin Povišer
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f44a418212
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read_xaiger2: Add casts to silence warnings
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2024-10-07 12:27:54 +02:00 |
Martin Povišer
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8d12492610
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read_xaiger2: Fix detecting the end of extensions
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2024-10-07 12:03:48 +02:00 |
Martin Povišer
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2b1b5652f1
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Adjust `read_xaiger2` prints
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2024-10-07 12:03:48 +02:00 |
rherveille
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ce7db661a8
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Added cast to type support (#4284)
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2024-09-29 17:03:01 -04:00 |
Martin Povišer
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f168b2f4b1
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read_xaiger2: Update box handling
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2024-09-18 16:55:02 +02:00 |
Martin Povišer
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1ab7f29933
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Start read_xaiger2 -sc_mapping
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2024-09-18 16:42:56 +02:00 |
Martin Povišer
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4976abb867
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read_liberty: Optionally import unit delay arcs
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2024-09-18 16:17:03 +02:00 |
N. Engelhardt
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c8b42b7d48
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Merge pull request #4538 from RCoeurjoly/verific_bounds
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2024-09-12 13:04:04 +02:00 |
Emil J. Tywoniak
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1372c47036
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internal_stats: astnode (sizeof)
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2024-09-11 11:34:20 +02:00 |
Roland Coeurjoly
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bdc43c6592
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Add left and right bound properties to wire. Add test. Fix printing
for signed attributes
Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
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2024-09-10 12:52:42 +02:00 |
Roland Coeurjoly
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27c1432253
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Remove log
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2024-08-21 14:28:42 +01:00 |
Roland Coeurjoly
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91e3773b51
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Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting
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2024-08-21 14:28:42 +01:00 |
Martin Povišer
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ab5d6b06b4
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read_liberty: Fix omitted helper change
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2024-08-13 20:12:38 +02:00 |
Martin Povišer
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309d80885b
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read_liberty: Use available gate creation helpers
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2024-08-13 18:47:36 +02:00 |
Martin Povišer
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3057c13a66
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Improve libparse encapsulation
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2024-08-13 18:47:36 +02:00 |
Miodrag Milanović
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3e14e67374
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Merge pull request #4500 from YosysHQ/micko/vhdl_mixcase
VHDL is case insensitive, make sure netlist name is proper
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2024-07-29 16:44:13 +02:00 |
Miodrag Milanovic
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405897a971
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Update top value that is returned back to hierarchy pass
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2024-07-29 15:50:38 +02:00 |
Miodrag Milanovic
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9566709426
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Initialize extensions when verific pass is registered
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2024-07-25 11:25:17 +02:00 |
Miodrag Milanovic
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c94aa719d9
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VHDL is case insensitive, make sure netlist name is proper
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2024-07-18 16:56:52 +02:00 |
Emil J. Tywoniak
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72a0380da8
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ast: don't suggest use in external projects
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2024-07-18 16:37:14 +02:00 |
gatecat
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22d8df1e7e
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liberty: Support for IO liberty files for verification
Signed-off-by: gatecat <gatecat@ds0.me>
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2024-06-19 21:12:42 +02:00 |
Miodrag Milanovic
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dfde792288
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Refactored import code
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2024-06-17 14:49:58 +02:00 |
Miodrag Milanovic
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19da7f7d59
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Update makefile to make options uniform
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2024-06-17 13:29:11 +02:00 |
Miodrag Milanovic
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0f3f731254
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Handle -work for vhdl, and clean messages
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2024-06-17 13:29:11 +02:00 |
Miodrag Milanovic
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0a81c8e161
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Import all modules from all libraries when when needed
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2024-06-17 13:29:11 +02:00 |
Miodrag Milanovic
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7c3094633d
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Compile with hier_tree separate SV and VHDL as well
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2024-06-17 13:29:11 +02:00 |
Miodrag Milanovic
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e2e189647f
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Cleanup
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2024-06-17 13:29:11 +02:00 |
Miodrag Milanovic
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7bec332b68
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SV + VHDL with RTL support
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2024-06-17 13:29:11 +02:00 |
Miodrag Milanovic
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25d50bb2af
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VHDL only build support
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2024-06-17 13:29:11 +02:00 |
Miodrag Milanovic
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54bf9ccf06
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Add initial support for Verific without additional YosysHQ patch
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2024-06-17 13:29:11 +02:00 |
Martin Povišer
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b593f5c01c
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Update the overview comment in `ast.h`
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2024-06-10 16:38:39 +02:00 |