riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Update top value that is returned back to hierarchy pass

This commit is contained in:
Miodrag Milanovic 2024-07-29 15:50:38 +02:00
parent c94aa719d9
commit 405897a971
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
frontends/verific/verific.cc
View File

@ -2760,7 +2760,7 @@ void import_all(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *
#endif
}
std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED, std::vector<std::string> &tops)
std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED, std::vector<std::string> &tops, std::string *top = nullptr)
{
std::set<std::string> top_mod_names;
Array *netlists = nullptr;
@ -2821,6 +2821,8 @@ std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist
if (strcmp(name, vhdl_unit->Id()->OrigName()) != 0) {
top_mod_names.erase(name);
top_mod_names.insert(vhdl_unit->Id()->OrigName());
if (top && *top == name)
*top = vhdl_unit->Id()->OrigName();
}
continue;
}
@ -2962,7 +2964,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
veri_file::RemoveAllLOptions();
veri_file::AddLOption("work");
#endif
top_mod_names = import_tops("work", &nl_todo, &verific_params, false, "", tops) ;
top_mod_names = import_tops("work", &nl_todo, &verific_params, false, "", tops, &top) ;
}
if (!verific_error_msg.empty())