mirror of https://github.com/YosysHQ/yosys.git
read_liberty: Start an `-ignore_busses` option
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0e96e477a2
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28aa7b00ee
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@ -462,6 +462,9 @@ struct LibertyFrontend : public Frontend {
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log(" -ignore_miss_data_latch\n");
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log(" ignore latches with missing data and/or enable pins\n");
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log("\n");
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log(" -ignore_busses\n");
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log(" ignore cells with bus interfaces (wide ports)\n");
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log("\n");
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log(" -setattr <attribute_name>\n");
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log(" set the specified attribute (to the value 1) on all loaded modules\n");
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log("\n");
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@ -478,6 +481,7 @@ struct LibertyFrontend : public Frontend {
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bool flag_ignore_miss_func = false;
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bool flag_ignore_miss_dir = false;
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bool flag_ignore_miss_data_latch = false;
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bool flag_ignore_busses = false;
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bool flag_unit_delay = false;
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std::vector<std::string> attributes;
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@ -514,6 +518,10 @@ struct LibertyFrontend : public Frontend {
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flag_ignore_miss_data_latch = true;
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continue;
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}
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if (arg == "-ignore_busses") {
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flag_ignore_busses = true;
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continue;
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}
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if (arg == "-setattr" && argidx+1 < args.size()) {
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attributes.push_back(RTLIL::escape_id(args[++argidx]));
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continue;
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@ -585,6 +593,12 @@ struct LibertyFrontend : public Frontend {
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if (node->id == "bus" && node->args.size() == 1)
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{
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if (flag_ignore_busses) {
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log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0).c_str());
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delete module;
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goto skip_cell;
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}
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if (!flag_lib)
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log_error("Error in cell %s: bus interfaces are only supported in -lib mode.\n", log_id(cell_name));
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