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Set VHDL assert condition initial state if fed by FF

This commit is contained in:
Miodrag Milanovic 2024-10-11 16:32:21 +02:00
parent 0200a7680a
commit 8d2b63bb8a
1 changed files with 6 additions and 7 deletions
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13
frontends/verific/verific.cc
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@ -2142,13 +2142,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
if (verific_verbose)
log(" assert condition %s.\n", log_signal(cond));
const char *assume_attr = nullptr; // inst->GetAttValue("assume");
Cell *cell = nullptr;
if (assume_attr != nullptr && !strcmp(assume_attr, "1"))
cell = module->addAssume(new_verific_id(inst), cond, State::S1);
else
cell = module->addAssert(new_verific_id(inst), cond, State::S1);
Cell *cell = module->addAssert(new_verific_id(inst), cond, State::S1);
// Initialize FF feeding condition to 1, in case it is not
// used by rest of design logic, to prevent failing on
// initial uninitialized state
if (cond.is_wire() && !cond.wire->name.isPublic())
cond.wire->attributes[ID::init] = Const(1,1);
import_attributes(cell->attributes, inst);
continue;