mirror of https://github.com/YosysHQ/yosys.git
Refactored import code
This commit is contained in:
Miodrag Milanovic
parent
19da7f7d59
commit
dfde792288
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@ -2696,183 +2696,217 @@ struct VerificExtNets
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}
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};
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std::string verific_import(Design *design, const std::map<std::string,std::string> ¶meters, std::string top)
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void import_all(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED)
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{
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verific_sva_fsm_limit = 16;
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#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
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VerificExtensions::ElaborateAndRewrite(work, parameters);
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verific_error_msg.clear();
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#endif
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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if (!ppfile.empty())
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veri_file::PrettyPrint(ppfile.c_str(), nullptr, work);
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#endif
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std::map<std::string,Netlist*> nl_todo, nl_done;
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Array *netlists = NULL;
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Array vhdl_libs;
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#ifdef VERIFIC_VHDL_SUPPORT
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VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1);
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VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work, 1);
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if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
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#endif
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Array veri_libs;
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1);
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VeriLibrary *veri_lib = veri_file::GetLibrary(work, 1);
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if (veri_lib) veri_libs.InsertLast(veri_lib);
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#endif
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Map verific_params(STRING_HASH);
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for (const auto &i : parameters)
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verific_params.Insert(i.first.c_str(), i.second.c_str());
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if (top.empty()) {
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#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
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VerificExtensions::ElaborateAndRewrite("work", &verific_params);
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verific_error_msg.clear();
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#endif
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#ifdef VERIFIC_HIER_TREE_SUPPORT
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netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params);
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if (show_message)
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log("Running hier_tree::ElaborateAll().\n");
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Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, parameters);
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Netlist *nl;
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int i;
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FOREACH_ARRAY_ITEM(netlists, i, nl)
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nl_todo->emplace(nl->CellBaseName(), nl);
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delete netlists;
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#else
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if (parameters.size())
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log_warning("Please note that parameters are not propagated during import.\n");
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if (parameters->Size())
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log_warning("Please note that parameters are not propagated during import.\n");
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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veri_file::ElaborateAll("work");
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if (show_message)
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log("Running veri_file::ElaborateAll().\n");
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veri_file::ElaborateAll(work);
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#endif
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#ifdef VERIFIC_VHDL_SUPPORT
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vhdl_file::ElaborateAll("work");
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if (show_message)
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log("Running vhdl_file::ElaborateAll().\n");
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vhdl_file::ElaborateAll(work);
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#endif
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netlists = new Array(1);
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MapIter mi ;
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Verific::Cell *c ;
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MapIter it ;
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Library *l ;
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FOREACH_LIBRARY_OF_LIBSET(Libset::Global(),it,l) {
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if (l == Library::Primitives() || l == Library::Operators()) continue;
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FOREACH_CELL_OF_LIBRARY(l,mi,c) {
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MapIter ni ;
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Netlist *nl;
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FOREACH_NETLIST_OF_CELL(c, ni, nl) {
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if (nl)
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netlists->InsertLast(nl);
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}
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MapIter mi ;
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Verific::Cell *c ;
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MapIter it ;
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Library *l ;
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FOREACH_LIBRARY_OF_LIBSET(Libset::Global(),it,l) {
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if (l == Library::Primitives() || l == Library::Operators()) continue;
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FOREACH_CELL_OF_LIBRARY(l,mi,c) {
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MapIter ni ;
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Netlist *nl;
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FOREACH_NETLIST_OF_CELL(c, ni, nl) {
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if (nl)
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nl_todo->emplace(nl->CellBaseName(), nl);
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}
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}
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#endif
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}
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else {
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#endif
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}
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std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED, std::vector<std::string> &tops)
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{
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std::set<std::string> top_mod_names;
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Array *netlists = nullptr;
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#ifdef VERIFIC_VHDL_SUPPORT
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VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work, 1);
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#endif
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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VeriLibrary* veri_lib = veri_file::GetLibrary(work, 1);
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#endif
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#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
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for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--)
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for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--)
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#endif
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{
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Array vhdl_units;
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Array veri_modules;
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for (std::string n : tops)
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{
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Array veri_modules;
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const char *name = n.c_str();
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top_mod_names.insert(name);
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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if (veri_lib) {
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VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1);
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if (veri_module) {
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VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr;
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if (veri_module) {
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if (veri_module->IsConfiguration()) {
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if (show_message)
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log("Adding Verilog configuration '%s' to elaboration queue.\n", name);
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veri_modules.InsertLast(veri_module);
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if (veri_module->IsConfiguration()) {
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VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
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VeriName *module_name = (VeriName*)cfg->GetTopModuleNames()->GetLast();
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top_mod_names.erase(name);
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VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
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VeriName *module_name;
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int i;
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FOREACH_ARRAY_ITEM(cfg->GetTopModuleNames(), i, module_name) {
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VeriLibrary *lib = veri_module->GetLibrary() ;
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if (module_name && module_name->IsHierName()) {
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VeriName *prefix = module_name->GetPrefix() ;
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const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
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if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ;
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if (work != lib_name) lib = veri_file::GetLibrary(lib_name, 1) ;
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}
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if (lib && module_name)
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top = lib->GetModule(module_name->GetName(), 1)->GetName();
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}
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}
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#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
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if (!static_elaborate)
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#endif
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{
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// Also elaborate all root modules since they may contain bind statements
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MapIter mi;
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FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
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if (!veri_module->IsRootModule()) continue;
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veri_modules.InsertLast(veri_module);
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top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName());
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}
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} else {
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if (show_message)
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log("Adding Verilog module '%s' to elaboration queue.\n", name);
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veri_modules.InsertLast(veri_module);
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}
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continue;
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}
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#endif
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Array vhdl_units;
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#ifdef VERIFIC_VHDL_SUPPORT
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if (vhdl_lib) {
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VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str());
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if (vhdl_unit)
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vhdl_units.InsertLast(vhdl_unit);
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}
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#endif
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#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
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if (static_elaborate) {
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VerificExtensions::ElaborateAndRewrite("work", &veri_modules, &vhdl_units, &verific_params);
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verific_error_msg.clear();
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VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr;
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if (vhdl_unit) {
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if (show_message)
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log("Adding VHDL unit '%s' to elaboration queue.\n", name);
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vhdl_units.InsertLast(vhdl_unit);
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continue;
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}
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#endif
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log_error("Can't find module/unit '%s'.\n", name);
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}
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#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
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if (static_elaborate) {
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VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, parameters);
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verific_error_msg.clear();
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#endif
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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if (!ppfile.empty())
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veri_file::PrettyPrint(ppfile.c_str(), nullptr, work);
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#endif
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#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
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continue;
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}
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#endif
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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const char *lib_name = nullptr;
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SetIter si;
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FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) {
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VeriLibrary* veri_lib = veri_file::GetLibrary(lib_name, 0);
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if (veri_lib) {
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// Also elaborate all root modules since they may contain bind statements
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MapIter mi;
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VeriModule *veri_module;
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FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
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if (!veri_module->IsRootModule()) continue;
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veri_modules.InsertLast(veri_module);
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}
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}
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}
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#endif
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#ifdef VERIFIC_HIER_TREE_SUPPORT
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netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params);
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if (show_message)
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log("Running hier_tree::Elaborate().\n");
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netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, parameters);
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#else
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#if defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && !defined(VERIFIC_VHDL_SUPPORT)
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// SystemVerilog support only
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netlists = veri_file::ElaborateMultipleTop(&veri_modules, &verific_params);
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if (show_message)
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log("Running veri_file::ElaborateMultipleTop().\n");
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// SystemVerilog support only
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netlists = veri_file::ElaborateMultipleTop(&veri_modules, parameters);
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#elif defined(VERIFIC_VHDL_SUPPORT) && !defined(VERIFIC_SYSTEMVERILOG_SUPPORT)
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// VHDL support only
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netlists = new Array(1);
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vhdl_file::Elaborate(top.c_str(), "work", 0, &verific_params);
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if (show_message)
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log("Running vhdl_file::Elaborate().\n");
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// VHDL support only
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netlists = new Array(top_mod_names.size());
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for (auto &name : top_mod_names) {
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vhdl_file::Elaborate(name.c_str(), work, 0, parameters);
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netlists->InsertLast(Netlist::PresentDesign());
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}
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#elif defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && defined(VERIFIC_VHDL_SUPPORT)
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// Both SystemVerilog and VHDL support
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if (veri_modules.Size()>0)
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netlists = veri_file::ElaborateMultipleTop(&veri_modules, &verific_params);
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else
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netlists = new Array(1);
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if (vhdl_units.Size()>0) {
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vhdl_file::Elaborate(top.c_str(), "work", 0, &verific_params);
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// Both SystemVerilog and VHDL support
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if (veri_modules.Size()>0) {
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if (show_message)
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log("Running veri_file::ElaborateMultipleTop().\n");
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netlists = veri_file::ElaborateMultipleTop(&veri_modules, parameters);
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} else
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netlists = new Array(1);
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if (vhdl_units.Size()>0) {
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if (show_message)
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log("Running vhdl_file::Elaborate().\n");
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for (auto &name : top_mod_names) {
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vhdl_file::Elaborate(name.c_str(), work, 0, parameters);
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netlists->InsertLast(Netlist::PresentDesign());
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}
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}
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#else
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#endif
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#endif
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}
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}
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Netlist *nl;
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int i;
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std::string cell_name = top;
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FOREACH_ARRAY_ITEM(netlists, i, nl) {
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if (!nl) continue;
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if (!top.empty() && nl->CellBaseName() != top)
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if (!top_mod_names.count(nl->CellBaseName()))
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continue;
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nl->AddAtt(new Att(" \\top", NULL));
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nl_todo.emplace(nl->CellBaseName(), nl);
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cell_name = nl->CellBaseName();
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nl_todo->emplace(nl->CellBaseName(), nl);
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}
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if (top.empty()) cell_name = top;
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delete netlists;
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return top_mod_names;
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}
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if (!verific_error_msg.empty())
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log_error("%s\n", verific_error_msg.c_str());
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for (auto nl : nl_todo)
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nl.second->ChangePortBusStructures(1 /* hierarchical */);
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VerificExtNets worker;
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for (auto nl : nl_todo)
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worker.run(nl.second);
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while (!nl_todo.empty()) {
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auto it = nl_todo.begin();
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Netlist *nl = it->second;
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if (nl_done.count(it->first) == 0) {
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VerificImporter importer(false, false, false, false, false, false, false);
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nl_done[it->first] = it->second;
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importer.import_netlist(design, nl, nl_todo, nl->CellBaseName() == cell_name);
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}
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nl_todo.erase(it);
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}
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void verific_cleanup()
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{
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#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
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VerificExtensions::Reset();
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#endif
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@ -2901,7 +2935,53 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
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verific_libexts.clear();
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#endif
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verific_import_pending = false;
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}
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std::string verific_import(Design *design, const std::map<std::string,std::string> ¶meters, std::string top)
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{
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verific_sva_fsm_limit = 16;
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std::map<std::string,Netlist*> nl_todo, nl_done;
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Map verific_params(STRING_HASH);
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for (const auto &i : parameters)
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verific_params.Insert(i.first.c_str(), i.second.c_str());
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std::set<std::string> top_mod_names;
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if (top.empty()) {
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import_all("work", &nl_todo, &verific_params, false, "");
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} else {
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std::vector<std::string> tops;
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tops.push_back(top);
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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veri_file::RemoveAllLOptions();
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veri_file::AddLOption("work");
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#endif
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top_mod_names = import_tops("work", &nl_todo, &verific_params, false, "", tops) ;
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}
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if (!verific_error_msg.empty())
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log_error("%s\n", verific_error_msg.c_str());
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for (auto nl : nl_todo)
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nl.second->ChangePortBusStructures(1 /* hierarchical */);
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VerificExtNets worker;
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for (auto nl : nl_todo)
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worker.run(nl.second);
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while (!nl_todo.empty()) {
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auto it = nl_todo.begin();
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Netlist *nl = it->second;
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if (nl_done.count(it->first) == 0) {
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VerificImporter importer(false, false, false, false, false, false, false);
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nl_done[it->first] = it->second;
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importer.import_netlist(design, nl, nl_todo, top_mod_names.count(nl->CellBaseName()));
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}
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nl_todo.erase(it);
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}
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verific_cleanup();
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if (!verific_error_msg.empty())
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log_error("%s\n", verific_error_msg.c_str());
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return top;
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@ -3974,203 +4054,17 @@ struct VerificPass : public Pass {
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if (mode_all)
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{
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#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
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VerificExtensions::ElaborateAndRewrite(work, ¶meters);
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verific_error_msg.clear();
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#endif
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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if (!ppfile.empty())
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veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str());
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#endif
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Array vhdl_libs;
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#ifdef VERIFIC_VHDL_SUPPORT
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VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
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if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
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#endif
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Array veri_libs;
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);
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if (veri_lib) veri_libs.InsertLast(veri_lib);
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#endif
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#ifdef VERIFIC_HIER_TREE_SUPPORT
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log("Running hier_tree::ElaborateAll().\n");
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Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, ¶meters);
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Netlist *nl;
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int i;
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FOREACH_ARRAY_ITEM(netlists, i, nl)
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nl_todo.emplace(nl->CellBaseName(), nl);
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delete netlists;
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#else
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if (parameters.Size())
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log_warning("Please note that parameters are not propagated during import.\n");
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
|
||||
log("Running veri_file::ElaborateAll().\n");
|
||||
veri_file::ElaborateAll(work.c_str());
|
||||
#endif
|
||||
#ifdef VERIFIC_VHDL_SUPPORT
|
||||
log("Running vhdl_file::ElaborateAll().\n");
|
||||
vhdl_file::ElaborateAll(work.c_str());
|
||||
#endif
|
||||
MapIter mi ;
|
||||
Verific::Cell *c ;
|
||||
MapIter it ;
|
||||
Library *l ;
|
||||
FOREACH_LIBRARY_OF_LIBSET(Libset::Global(),it,l) {
|
||||
if (l == Library::Primitives() || l == Library::Operators()) continue;
|
||||
FOREACH_CELL_OF_LIBRARY(l,mi,c) {
|
||||
MapIter ni ;
|
||||
Netlist *nl;
|
||||
FOREACH_NETLIST_OF_CELL(c, ni, nl) {
|
||||
if (nl)
|
||||
nl_todo.emplace(nl->CellBaseName(), nl);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
import_all(work.c_str(), &nl_todo, ¶meters, true, ppfile);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (argidx == GetSize(args))
|
||||
cmd_error(args, argidx, "No top module specified.\n");
|
||||
|
||||
Array *netlists = nullptr;
|
||||
|
||||
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
|
||||
for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--)
|
||||
#endif
|
||||
{
|
||||
|
||||
Array vhdl_units;
|
||||
#ifdef VERIFIC_VHDL_SUPPORT
|
||||
VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
|
||||
#endif
|
||||
Array veri_modules;
|
||||
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
|
||||
VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
|
||||
#endif
|
||||
for (int i = argidx; i < GetSize(args); i++)
|
||||
{
|
||||
const char *name = args[i].c_str();
|
||||
top_mod_names.insert(name);
|
||||
|
||||
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
|
||||
VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr;
|
||||
if (veri_module) {
|
||||
if (veri_module->IsConfiguration()) {
|
||||
log("Adding Verilog configuration '%s' to elaboration queue.\n", name);
|
||||
veri_modules.InsertLast(veri_module);
|
||||
|
||||
top_mod_names.erase(name);
|
||||
|
||||
VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
|
||||
VeriName *module_name;
|
||||
int i;
|
||||
FOREACH_ARRAY_ITEM(cfg->GetTopModuleNames(), i, module_name) {
|
||||
VeriLibrary *lib = veri_module->GetLibrary() ;
|
||||
if (module_name && module_name->IsHierName()) {
|
||||
VeriName *prefix = module_name->GetPrefix() ;
|
||||
const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
|
||||
if (work != lib_name) lib = veri_file::GetLibrary(lib_name, 1) ;
|
||||
}
|
||||
if (lib && module_name)
|
||||
top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName());
|
||||
}
|
||||
} else {
|
||||
log("Adding Verilog module '%s' to elaboration queue.\n", name);
|
||||
veri_modules.InsertLast(veri_module);
|
||||
}
|
||||
continue;
|
||||
}
|
||||
#endif
|
||||
#ifdef VERIFIC_VHDL_SUPPORT
|
||||
VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr;
|
||||
if (vhdl_unit) {
|
||||
log("Adding VHDL unit '%s' to elaboration queue.\n", name);
|
||||
vhdl_units.InsertLast(vhdl_unit);
|
||||
continue;
|
||||
}
|
||||
#endif
|
||||
log_error("Can't find module/unit '%s'.\n", name);
|
||||
}
|
||||
|
||||
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
|
||||
if (static_elaborate) {
|
||||
VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, ¶meters);
|
||||
verific_error_msg.clear();
|
||||
#endif
|
||||
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
|
||||
if (!ppfile.empty())
|
||||
veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str());
|
||||
#endif
|
||||
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
|
||||
continue;
|
||||
}
|
||||
#endif
|
||||
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
|
||||
const char *lib_name = nullptr;
|
||||
SetIter si;
|
||||
FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) {
|
||||
VeriLibrary* veri_lib = veri_file::GetLibrary(lib_name, 0);
|
||||
if (veri_lib) {
|
||||
// Also elaborate all root modules since they may contain bind statements
|
||||
MapIter mi;
|
||||
VeriModule *veri_module;
|
||||
FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
|
||||
if (!veri_module->IsRootModule()) continue;
|
||||
veri_modules.InsertLast(veri_module);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#ifdef VERIFIC_HIER_TREE_SUPPORT
|
||||
log("Running hier_tree::Elaborate().\n");
|
||||
netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, ¶meters);
|
||||
#else
|
||||
#if defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && !defined(VERIFIC_VHDL_SUPPORT)
|
||||
log("Running veri_file::ElaborateMultipleTop().\n");
|
||||
// SystemVerilog support only
|
||||
netlists = veri_file::ElaborateMultipleTop(&veri_modules, ¶meters);
|
||||
#elif defined(VERIFIC_VHDL_SUPPORT) && !defined(VERIFIC_SYSTEMVERILOG_SUPPORT)
|
||||
log("Running vhdl_file::Elaborate().\n");
|
||||
// VHDL support only
|
||||
netlists = new Array(top_mod_names.size());
|
||||
for (auto &name : top_mod_names) {
|
||||
vhdl_file::Elaborate(name.c_str(), work.c_str(), 0, ¶meters);
|
||||
netlists->InsertLast(Netlist::PresentDesign());
|
||||
}
|
||||
#elif defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && defined(VERIFIC_VHDL_SUPPORT)
|
||||
// Both SystemVerilog and VHDL support
|
||||
if (veri_modules.Size()>0) {
|
||||
log("Running veri_file::ElaborateMultipleTop().\n");
|
||||
netlists = veri_file::ElaborateMultipleTop(&veri_modules, ¶meters);
|
||||
} else
|
||||
netlists = new Array(1);
|
||||
if (vhdl_units.Size()>0) {
|
||||
log("Running vhdl_file::Elaborate().\n");
|
||||
for (auto &name : top_mod_names) {
|
||||
vhdl_file::Elaborate(name.c_str(), work.c_str(), 0, ¶meters);
|
||||
netlists->InsertLast(Netlist::PresentDesign());
|
||||
}
|
||||
}
|
||||
#else
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
Netlist *nl;
|
||||
int i;
|
||||
|
||||
FOREACH_ARRAY_ITEM(netlists, i, nl) {
|
||||
if (!nl) continue;
|
||||
if (!top_mod_names.count(nl->CellBaseName()))
|
||||
continue;
|
||||
nl->AddAtt(new Att(" \\top", NULL));
|
||||
nl_todo.emplace(nl->CellBaseName(), nl);
|
||||
}
|
||||
delete netlists;
|
||||
std::vector<std::string> tops;
|
||||
for (int i = argidx; i < GetSize(args); i++)
|
||||
tops.push_back(args[i].c_str());
|
||||
top_mod_names = import_tops(work.c_str(), &nl_todo, ¶meters, true, ppfile, tops) ;
|
||||
}
|
||||
if (mode_cells) {
|
||||
log("Importing all cells.\n");
|
||||
|
|
@ -4232,34 +4126,7 @@ struct VerificPass : public Pass {
|
|||
nl_todo.erase(it);
|
||||
}
|
||||
|
||||
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
|
||||
VerificExtensions::Reset();
|
||||
#endif
|
||||
#ifdef VERIFIC_HIER_TREE_SUPPORT
|
||||
hier_tree::DeleteHierarchicalTree();
|
||||
#endif
|
||||
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
|
||||
veri_file::Reset();
|
||||
#endif
|
||||
#ifdef VERIFIC_VHDL_SUPPORT
|
||||
vhdl_file::Reset();
|
||||
#endif
|
||||
#ifdef VERIFIC_EDIF_SUPPORT
|
||||
edif_file::Reset();
|
||||
#endif
|
||||
#ifdef VERIFIC_LIBERTY_SUPPORT
|
||||
synlib_file::Reset();
|
||||
#endif
|
||||
Libset::Reset();
|
||||
Message::Reset();
|
||||
RuntimeFlags::DeleteAllFlags();
|
||||
LineFile::DeleteAllLineFiles();
|
||||
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
|
||||
verific_incdirs.clear();
|
||||
verific_libdirs.clear();
|
||||
verific_libexts.clear();
|
||||
#endif
|
||||
verific_import_pending = false;
|
||||
verific_cleanup();
|
||||
goto check_error;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue