mirror of https://github.com/YosysHQ/yosys.git
Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting
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4cddc19994
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@ -51,6 +51,9 @@ void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int wi
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}
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}
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f << stringf("%d'", width);
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if (data.flags & RTLIL::CONST_FLAG_SIGNED) {
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f << stringf("s");
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}
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if (data.is_fully_undef_x_only()) {
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f << "x";
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} else {
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@ -88,7 +88,7 @@ USING_YOSYS_NAMESPACE
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"\\"[^ \t\r\n]+ { rtlil_frontend_yylval.string = strdup(yytext); return TOK_ID; }
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"$"[^ \t\r\n]+ { rtlil_frontend_yylval.string = strdup(yytext); return TOK_ID; }
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[0-9]+'[01xzm-]* { rtlil_frontend_yylval.string = strdup(yytext); return TOK_VALUE; }
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[0-9]+'s?[01xzm-]* { rtlil_frontend_yylval.string = strdup(yytext); return TOK_VALUE; }
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-?[0-9]+ {
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char *end = nullptr;
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errno = 0;
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@ -412,8 +412,16 @@ constant:
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TOK_VALUE {
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char *ep;
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int width = strtol($1, &ep, 10);
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bool is_signed = false;
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if (*ep == '\'') {
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ep++;
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}
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if (*ep == 's') {
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is_signed = true;
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ep++;
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}
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std::list<RTLIL::State> bits;
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while (*(++ep) != 0) {
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while (*ep != 0) {
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RTLIL::State bit = RTLIL::Sx;
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switch (*ep) {
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case '0': bit = RTLIL::S0; break;
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@ -424,7 +432,9 @@ constant:
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case 'm': bit = RTLIL::Sm; break;
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}
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bits.push_front(bit);
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ep++;
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}
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if (bits.size() == 0)
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bits.push_back(RTLIL::Sx);
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while ((int)bits.size() < width) {
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@ -438,6 +448,10 @@ constant:
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$$ = new RTLIL::Const;
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for (auto it = bits.begin(); it != bits.end(); it++)
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$$->bits.push_back(*it);
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if (is_signed) {
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$$->flags |= RTLIL::CONST_FLAG_SIGNED;
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log("Setting SIGNED flag for constant with width %d\n", width);
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}
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free($1);
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} |
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TOK_INT {
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@ -0,0 +1,10 @@
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! mkdir -p temp
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read_rtlil <<EOT
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module \test
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attribute \bottom_bound 3's101
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wire width 3 output 1 \a
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connect \a 3'001
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end
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EOT
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write_rtlil temp/rtlil_signed_attribute.il
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! grep -F -q "attribute \bottom_bound 3's101" temp/rtlil_signed_attribute.il
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