mirror of https://github.com/YosysHQ/yosys.git
read_liberty: Set `area` `capacitance` attributes
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@ -571,6 +571,10 @@ struct LibertyFrontend : public Frontend {
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if (flag_wb)
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module->set_bool_attribute(ID::whitebox);
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const LibertyAst *area = cell->find("area");
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if (area)
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module->attributes[ID::area] = area->value;
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for (auto &attr : attributes)
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module->attributes[attr] = 1;
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@ -662,6 +666,10 @@ struct LibertyFrontend : public Frontend {
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RTLIL::Wire *wire = module->wires_.at(RTLIL::escape_id(node->args.at(0)));
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log_assert(wire);
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const LibertyAst *capacitance = node->find("capacitance");
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if (capacitance)
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wire->attributes[ID::capacitance] = capacitance->value;
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if (dir && dir->value == "inout") {
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wire->port_input = true;
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wire->port_output = true;
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@ -274,3 +274,5 @@ X(X)
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X(xprop_decoder)
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X(Y)
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X(Y_WIDTH)
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X(area)
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X(capacitance)
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