riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
4,617 Commits 84 Branches 48 Tags 64 MiB
Commit Graph

87 Commits

Author SHA1 Message Date
Eddie Hung d9cb787391 synth_xilinx to map_cells before map_luts 2019-04-04 07:48:13 -07:00
David Shah 46f6a60d58 xilinx: Add keep attribute where appropriate 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 13:57:17 +00:00
Clifford Wolf fe1fb1336b Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-19 20:30:28 +01:00
Clifford Wolf bfcd46dbd3
Merge pull request #842 from litghost/merge_upstream 
Changes required for VPR place and route in synth_xilinx
 2019-03-05 15:33:19 -08:00
Clifford Wolf 13844c7658 Use "write_edif -pvector bra" for Xilinx EDIF files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-05 15:16:13 -08:00
Keith Rothman 228f132ec3 Revert BRAM WRITE_MODE changes. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-04 09:22:22 -08:00
Keith Rothman 3e16f75bc6 Revert FF models to include IS_x_INVERTED parameters. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 14:41:21 -08:00
Keith Rothman 5ebeca12eb Use singular for disabling of DRAM or BRAM inference. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 14:35:14 -08:00
Keith Rothman eccaf101d8 Modify arguments to match existing style. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 12:14:27 -08:00
Keith Rothman 3090951d54 Changes required for VPR place and route synth_xilinx. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 12:02:27 -08:00
whitequark efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
Eddie Hung 99a14b0e37 Add support for Xilinx PS7 block 2018-11-10 12:45:07 -08:00
Tim 'mithro' Ansell b111ea1228 xilinx: Still map LUT7/LUT8 to Xilinx specific primitives. 
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
 2018-10-08 16:52:12 -07:00
Clifford Wolf 5f1fea08d5 Add inout ports to cells_xtra.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-04 11:30:55 +02:00
Tim Ansell ad975fb694
xilinx: Adding missing inout IO port to IOBUF 2018-10-03 16:38:32 -07:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Tim 'mithro' Ansell d6bdefd2e9 Improving vpr output support. 
* Support output BLIF for Xilinx architectures.
 * Support using .names in BLIF for Xilinx architectures.
 * Use the same `NO_LUT` define in both `synth_ice40` and
  `synth_xilinx`.
 2018-04-18 16:55:12 -07:00
Larry Doolittle efaef82f75 Squelch trailing whitespace, including meta-whitespace 2018-03-11 16:03:41 +01:00
Clifford Wolf 6991c132b5 Add Xilinx RAM64X1D and RAM128X1D simulation models 2018-03-07 17:31:48 +01:00
Clifford Wolf 8a69759306 Add techlibs/xilinx/lut2lut.v 2017-07-10 12:09:05 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf ff5c61b120 Added black box modules for all the 7-series design elements (as listed in ug953) 2016-03-19 11:09:10 +01:00
Clifford Wolf a75f94ec4a Run dffsr2dff in synth_xilinx 2016-02-13 08:20:19 +01:00
Clifford Wolf 17372d8abd Added "abc -luts" option, Improved Xilinx logic mapping 2016-02-01 12:40:32 +01:00
Clifford Wolf 864808992b Bugfix in Xilinx LUT mapping 2015-10-30 13:58:03 +01:00
Clifford Wolf f42218682d Added examples/ top-level directory 2015-10-13 15:41:20 +02:00
Clifford Wolf 924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf c475deec6c Switched to Python 3 2015-08-22 09:59:33 +02:00
Clifford Wolf 9596fe74de Another bugfix for ice40 and xilinx brams_init make rules 2015-08-16 21:39:34 +02:00
Clifford Wolf aedcfd6fd3 Fixed Makefile rules for generated share files 2015-08-16 21:15:07 +02:00
Clifford Wolf e4ef000b70 Adjust makefiles to work with out-of-tree builds 
This is based on work done by Larry Doolittle
 2015-08-12 15:04:44 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf c329233f0d Added output args to synth_ice40 2015-05-26 17:08:53 +02:00
Clifford Wolf 61512b6f41 Verific build fixes 2015-05-17 08:19:52 +02:00
Clifford Wolf 3481f46d1e Improved xilinx "bram1" test 2015-04-09 17:12:12 +02:00
Clifford Wolf 7319951145 Added memory_bram "make_outreg" feature 2015-04-09 16:08:54 +02:00
Clifford Wolf 229825e1b8 Xilinx DRAMS: RAM64X1D, RAM128X1D 2015-04-09 13:37:07 +02:00
Clifford Wolf b00cad81d7 Towards DRAM support in Xilinx flow 2015-04-09 08:17:14 +02:00
Clifford Wolf 8520b7fbe0 Added support for initialized xilinx brams 2015-04-06 17:07:10 +02:00
Clifford Wolf d19866615b Added Xilinx test case for initialized brams 2015-04-06 13:27:11 +02:00
Clifford Wolf 4389d9306e Added Xilinx bram black-box modules 2015-04-06 08:44:30 +02:00
Clifford Wolf c52a4cdeed Added "dffinit", Support for initialized Xilinx DFF 2015-04-04 19:00:15 +02:00
Clifford Wolf 4d34d031f9 Added "stat" to "synth" and "synth_xilinx" 2015-02-15 13:25:15 +01:00
Clifford Wolf 881dcd8af9 Added final checks to "synth" and "synth_xilinx" 2015-02-15 13:00:00 +01:00
Clifford Wolf 853e949c0e Disabled (unused) Xilinx tristate buffers 2015-02-04 16:33:59 +01:00
Clifford Wolf bebbf2e5a4 no support for 6-series xilinx devices 2015-02-01 23:06:44 +01:00
Clifford Wolf 3cbfa3815e Removed old XST-based xilinx examples 2015-02-01 17:10:46 +01:00
Clifford Wolf 816fe6bbe0 Added Xilinx example for Basys3 board 2015-02-01 17:09:34 +01:00
Clifford Wolf 1b159bc955 Added missing ports and parameters to xilinx brams 2015-02-01 15:42:59 +01:00
Clifford Wolf 909a95182b Fixed xilinx FDSE sim model 2015-01-24 11:03:22 +01:00