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8273 Commits

Author SHA1 Message Date
Rodrigo Alejandro Melo e9dc2759c4 Fixed some missing "verilog_" in documentation 2019-12-13 10:17:05 -03:00
N. Engelhardt ce3615b367 add periods and newlines to help message 2019-12-13 10:28:34 +01:00
Eddie Hung d0ee4cd88f Remove extraneous synth_xilinx call 2019-12-12 19:00:26 -08:00
Eddie Hung 01116f0f0a Add tests for these new models 2019-12-12 18:52:48 -08:00
Eddie Hung 8925bf4b96 Add RAM32X6SDP and RAM64X3SDP modes 2019-12-12 18:52:28 -08:00
Eddie Hung 50e0c83560 Fix RAM64M model to have 6 bit address bus 2019-12-12 18:52:03 -08:00
Eddie Hung 037d1a03df Add #1460 testcase 2019-12-12 17:49:55 -08:00
Eddie Hung 7a9d1be97d Add memory rules for RAM16X1D, RAM32M, RAM64M 2019-12-12 17:44:59 -08:00
Eddie Hung caab66111e Rename memory tests to lutram, add more xilinx tests 2019-12-12 17:44:37 -08:00
Diego H 751a18d7e9 Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. 2019-12-12 17:32:58 -06:00
Eddie Hung fce6bad6ae Remove 'clkpart' entry in CHANGELOG 2019-12-12 15:02:46 -08:00
Eddie Hung bea15b537b Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-12 14:57:17 -08:00
Eddie Hung 9ab1feeaf1 abc9_map.v: fix Xilinx LUTRAM 2019-12-12 14:56:52 -08:00
Eddie Hung 3eed8835b5 abc9_map.v: fix Xilinx LUTRAM 2019-12-12 14:56:15 -08:00
Diego H e33f407655 Adding a note (TODO) in the memory_params.ys check file 2019-12-12 16:06:46 -06:00
N. Engelhardt 1187e91c2f add test and make help message more verbose 2019-12-12 20:51:59 +01:00
Diego H 937ec1ee78 Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 2019-12-12 13:50:36 -06:00
Diego H ab6ac8327f Merge https://github.com/YosysHQ/yosys into bram_xilinx 2019-12-12 13:40:05 -06:00
Eddie Hung 23fcfd0adb Make SV2017 compliant courtesy of @wsnyder 2019-12-12 07:34:07 -08:00
N. Engelhardt 4c7cda1c8b add a command to read/modify scratchpad contents 2019-12-12 16:25:03 +01:00
Eddie Hung 1ac1697e15 Stray log_dump 2019-12-11 16:59:00 -08:00
Eddie Hung af36943cb9 Preserve size of $genval$-s in for loops 2019-12-11 16:52:37 -08:00
Eddie Hung 151f7533e8 Add testcase 2019-12-11 16:52:37 -08:00
Eddie Hung 2666482282 Update README.md :: abc_ -> abc9_ 2019-12-11 16:38:43 -08:00
Eddie Hung f022645cd2 Fix bitwidth mismatch; suppresses iverilog warning 2019-12-11 13:02:07 -08:00
Gustavo Romero 993a77d19b manual: Fix text in Abstract section 2019-12-11 08:22:08 -03:00
David Shah 613334d9dc
Merge pull request #1564 from ZirconiumX/intel_housekeeping 
Intel housekeeping
 2019-12-11 08:46:10 +00:00
Dan Ravensloft 85a14895ca synth_intel: a10gx -> arria10gx 2019-12-10 13:48:10 +00:00
Dan Ravensloft eab3272cde synth_intel: cyclone10 -> cyclone10lp 2019-12-10 13:47:58 +00:00
Eddie Hung 7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr 
Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
 2019-12-09 17:38:48 -08:00
Eddie Hung 49c2e59b2a Fix comment 2019-12-09 15:44:19 -08:00
Eddie Hung fb203d2a2c ice40_opt to restore attributes/name when unwrapping 2019-12-09 14:29:29 -08:00
Eddie Hung 36a88be609 ice40_wrapcarry -unwrap to preserve 'src' attribute 2019-12-09 14:28:54 -08:00
Eddie Hung eff858cd33 unmap $__ICE40_CARRY_WRAPPER in test 2019-12-09 14:20:35 -08:00
Eddie Hung bbdf2452b3 -unwrap to create $lut not SB_LUT4 for opt_lut 2019-12-09 13:27:09 -08:00
Eddie Hung 500ed9b501 Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4 2019-12-09 12:45:22 -08:00
Eddie Hung e05372778a ice40_wrapcarry to really preserve attributes via -unwrap option 2019-12-09 11:48:28 -08:00
David Shah 184c0e796a ecp5: Add support for mapping PRLD FFs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-07 13:04:36 +00:00
Eddie Hung a46a7e8a67 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-06 23:22:52 -08:00
Eddie Hung ecb0c68f07
Merge pull request #1555 from antmicro/fix-macc-xilinx-test 
tests: arch: xilinx: Change order of arguments in macc.sh
 2019-12-06 23:04:04 -08:00
Eddie Hung 946d5854c0 Drop keep=0 attributes on SB_CARRY 2019-12-06 17:27:47 -08:00
Eddie Hung 91467938c4 Stray newline 2019-12-06 17:08:19 -08:00
Eddie Hung f2ac36de4a write_xaiger to inst each cell type once, do not call techmap/aigmap 2019-12-06 17:06:10 -08:00
Eddie Hung 98c9ea605b techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger 2019-12-06 17:05:02 -08:00
Eddie Hung ab667d3d47 Call abc9 with "&write -n", and parse_xaiger() to cope 2019-12-06 16:35:57 -08:00
Eddie Hung c767525441 Remove creation of $abc9_control_wire 2019-12-06 16:23:09 -08:00
Eddie Hung 69d8c1386a Do not connect undriven POs to 1'bx 2019-12-06 16:21:06 -08:00
Eddie Hung fce527f4f7 Fix abc9 re-integration, remove abc9_control_wire, use cell->type as 
as part of clock domain for mergeability class
 2019-12-06 16:20:18 -08:00
Eddie Hung 1f96de04c9 Fix writing non-whole modules, including inouts and keeps 2019-12-06 16:19:10 -08:00
Jan Kowalewski dcb30b5f4a tests: arch: xilinx: Change order of arguments in macc.sh 2019-12-06 09:15:49 +01:00