riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
9,534 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

9534 Commits

Author SHA1 Message Date
whitequark 2b1fb8c0a0
Merge pull request #1967 from whitequark/cxxrtl-blackbox-attributes 
cxxrtl: provide attributes to black box factories, too
 2020-04-19 19:59:42 +00:00
whitequark bf0f96b847 cxxrtl: provide attributes to black box factories, too. 
Both parameters and attributes are necessary because the parameters
have to be the same between every instantiation of the cell, but
attributes may well vary. For example, for an UART PHY, the type
of the PHY (tty, pty, socket) would be a parameter, but configuration
of the implementation specified by the type (socket address) would
be an attribute.
 2020-04-19 16:30:54 +00:00
Claire Wolf 35990b95ec Extend support for format strings in Verilog front-end 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-18 14:08:51 +02:00
whitequark c98cde8842
Merge pull request #1963 from whitequark/cxxrtl-blackboxes 
cxxrtl: add support for simple and templated C++ black boxes
 2020-04-18 09:21:14 +00:00
whitequark 63d2a30857 cxxrtl: add templated black box support. 2020-04-18 08:04:57 +00:00
whitequark ab4297c326 cxxrtl: make eval() and commit() inline in blackboxes. 
This change is a preparation for template blackboxes. It has no
effect on current generated code.
 2020-04-18 04:38:50 +00:00
whitequark 2b88d9a3fe cxxrtl: add simple black box support. 
This commit adds support for replacing RTLIL modules with CXXRTL
black boxes. Black box port widths may not depend on the parameters
with which it is instantiated (yet); the parameters may only be used
to change the behavior of the black box.
 2020-04-18 04:35:10 +00:00
whitequark 8bc3cd30dc cxxrtl: use ID::X instead of ID(X). NFC. 2020-04-18 04:35:10 +00:00
whitequark 41421f5dca ast, rpc: record original name of $paramod\* as \hdlname attribute. 
The $paramod name mangling is not invertible (the \ character, which
separates the module name from the parameters, is valid in the module
name itself), which does not stop people from trying to invert it.

This commit makes it easy to invert the name mangling by storing
the original name explicitly, and fixes the firrtl backend to use
the newly introduced attribute.
 2020-04-18 03:47:28 +00:00
whitequark d42530b7bb
Merge pull request #1955 from whitequark/cxxrtl-sync_always 
cxxrtl: correctly handle `sync always` rules
 2020-04-17 21:36:59 +00:00
whitequark 67fbc00a18
Merge pull request #1952 from boqwxp/add_edge_location 
Verilog frontend: add source location in more parser rules
 2020-04-17 18:57:00 +00:00
diego 50581d5a94 Wrong fixed value 2020-04-17 10:15:22 -05:00
whitequark e7ad209b15 cxxrtl: correctly handle `sync always` rules. 
Fixes #1948.
 2020-04-17 09:43:13 +00:00
whitequark 115fc261e6
Merge pull request #1954 from YosysHQ/dave/fix-stdout-conflict 
qbfsat: Fix illegal use of 'stdout' identifier
 2020-04-17 09:07:49 +00:00
whitequark 4d1db12133
Merge pull request #1951 from whitequark/rtlil-string_attribute 
rtlil: add AttrObject::{get,set}_string_attribute, AttrObject::has_attribute
 2020-04-17 09:06:40 +00:00
David Shah 586739ecf3 qbfsat: Fix illegal use of 'stdout' identifier 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-17 08:42:39 +01:00
Alberto Gonzalez 00d74f0b9c
Set Verilog source location for explicit blocks (`begin` ... `end`). 2020-04-17 06:23:03 +00:00
Alberto Gonzalez 10a814f978
Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes. 2020-04-17 06:16:59 +00:00
whitequark c69db910ac
Merge pull request #1898 from boqwxp/locations 
Verilog frontend: add location information to parsed constants
 2020-04-17 02:27:13 +00:00
whitequark 69743aad42
Merge pull request #1864 from boqwxp/cleanup_techmap_abc 
Clean up pseudo-private member usage and simplify `passes/techmap/abc.cc`
 2020-04-17 02:25:18 +00:00
whitequark f2064c8131
Merge pull request #1888 from boqwxp/cleanup_scatter 
Clean up `passes/cmds/scatter.cc`.
 2020-04-17 02:21:23 +00:00
whitequark 5c428996a9
Merge pull request #1882 from boqwxp/cleanup_rename 
Clean up pseudo-private member usage in `passes/cmds/rename.cc`.
 2020-04-17 02:20:54 +00:00
whitequark 31e3e52988
Merge pull request #1929 from YosysHQ/eddie/select_unset 
select: add select -unset option
 2020-04-16 22:09:25 +00:00
whitequark b6f624b56b rtlil: add AttrObject::has_attribute. 2020-04-16 21:49:49 +00:00
whitequark ff7a1a1568 rtlil: add AttrObject::{get,set}_string_attribute. 
And make {get,set}_src_attribute use those functions.
 2020-04-16 21:45:29 +00:00
whitequark b4b2345a10
Merge pull request #1947 from whitequark/cxxrtl-usability 
cxxrtl: minor documentation and usability improvements
 2020-04-16 21:28:13 +00:00
Eddie Hung 9eace8f360 design: add test 2020-04-16 12:48:40 -07:00
Eddie Hung dac5adde12 design: -import to not count black/white-boxes as candidates for top 2020-04-16 12:46:07 -07:00
Eddie Hung 2ddfb61e65 select: add test for not selecting inside black/white boxes 2020-04-16 12:45:04 -07:00
Eddie Hung 47c8ee7fe4 select: do not select inside blackboxes 2020-04-16 12:23:34 -07:00
Alberto Gonzalez 9253497358
Add location information to `AST_CONSTANT` nodes. 2020-04-16 19:11:47 +00:00
Alberto Gonzalez 2e3647f567
Use `dict` instead of `std::map`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-04-16 18:56:50 +00:00
Alberto Gonzalez b94f38295a
Revert to `stringf()` rather than stringstreams. 2020-04-16 18:56:50 +00:00
Alberto Gonzalez 6081c1bbd3
Clean up pseudo-private member usage in `passes/cmds/rename.cc`. 2020-04-16 18:56:50 +00:00
Alberto Gonzalez ff8be2364e
Replace `std::map` with `dict`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-04-16 18:49:55 +00:00
Alberto Gonzalez 0424555702
Replace pseudo-private member access to `connections_` in `passes/cmds/scatter.cc`. 
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
 2020-04-16 18:49:55 +00:00
Alberto Gonzalez 0787af947f
Clean up `passes/cmds/scatter.cc`. 2020-04-16 18:49:55 +00:00
diego 87910732f1 Adding tests for dynamic part select optimisation 2020-04-16 13:31:05 -05:00
Eddie Hung 2623e335cc tests: add select -unset tests 2020-04-16 10:51:58 -07:00
Eddie Hung 254d38ca67 select: add select -unset option 2020-04-16 10:51:58 -07:00
Eddie Hung 8d3f6d0d79
Merge pull request #1928 from YosysHQ/eddie/design_delete 
kernel: add design -delete option
 2020-04-16 10:51:09 -07:00
whitequark c2804a68c2
Merge pull request #1896 from boqwxp/read_stdin_repl 
Frontend: allow reading file input from stdin, like a REPL heredoc mode
 2020-04-16 17:18:29 +00:00
Claire Wolf 7a434cdd7b
Merge pull request #1797 from epfl-vlsc/firrtl_backend_fileinfo 
Keep file information when emitting firrtl
 2020-04-16 18:50:43 +02:00
whitequark 06c0338f2c cxxrtl: make ROMs writable, document memory::operator[]. 
There is no practical benefit from using `const memory` for ROMs;
it uses an std::vector internally, which prevents contemporary
compilers from constant-propagating ROM contents. (It is not clear
whether they are permitted to do so.)

However, there is a major benefit from using non-const `memory` for
ROMs, which is the ability to dynamically fill the ROM for each
individual simulation.
 2020-04-16 16:45:54 +00:00
whitequark 9043632dcc cxxrtl: fix misleading example, caution about race conditions. 
Fixes #1944.
 2020-04-16 16:45:54 +00:00
whitequark 58e89cd368 cxxrtl: remove inaccurate comment. NFC. 2020-04-16 16:45:54 +00:00
David Shah 1664bcda12 ecp5: Force SIGNED ports to be 1 bit 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-16 16:38:19 +01:00
Eddie Hung aa552cefa3
Merge pull request #1927 from YosysHQ/eddie/design_remove_assert 
kernel: Design::remove(RTLIL::Module *) to check refcount_modules_
 2020-04-16 08:06:12 -07:00
Eddie Hung e8a841467f tests: add design -delete tests 2020-04-16 08:05:18 -07:00
Eddie Hung a9ec0defb9 kernel: add design -delete option 2020-04-16 08:05:18 -07:00