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Merge pull request #1952 from boqwxp/add_edge_location 

Verilog frontend: add source location in more parser rules
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whitequark 2020-04-17 18:57:00 +00:00 committed by GitHub
parent 115fc261e6 00d74f0b9c
commit 67fbc00a18
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1 changed files with 3 additions and 0 deletions
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3
frontends/verilog/verilog_parser.y
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@ -1924,11 +1924,13 @@ always_events:
always_event:
TOK_POSEDGE expr {
AstNode *node = new AstNode(AST_POSEDGE);
SET_AST_NODE_LOC(node, @1, @1);
ast_stack.back()->children.push_back(node);
node->children.push_back($2);
} |
TOK_NEGEDGE expr {
AstNode *node = new AstNode(AST_NEGEDGE);
SET_AST_NODE_LOC(node, @1, @1);
ast_stack.back()->children.push_back(node);
node->children.push_back($2);
} |
@ -2244,6 +2246,7 @@ behavioral_stmt:
exitTypeScope();
if ($4 != NULL && $8 != NULL && *$4 != *$8)
frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1);
SET_AST_NODE_LOC(ast_stack.back(), @2, @8);
delete $4;
delete $8;
ast_stack.pop_back();