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Merge pull request #1955 from whitequark/cxxrtl-sync_always 

cxxrtl: correctly handle `sync always` rules
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whitequark 2020-04-17 21:36:59 +00:00 committed by GitHub
parent 67fbc00a18 e7ad209b15
commit d42530b7bb
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1 changed files with 13 additions and 3 deletions
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16
backends/cxxrtl/cxxrtl.cc
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@ -1076,24 +1076,34 @@ struct CxxrtlWorker {
log_assert(proc->root_case.attributes.empty());
dump_case_rule(&proc->root_case);
for (auto sync : proc->syncs) {
RTLIL::SigBit sync_bit = sync->signal[0];
sync_bit = sigmaps[sync_bit.wire->module](sync_bit);
RTLIL::SigBit sync_bit;
if (!sync->signal.empty()) {
sync_bit = sync->signal[0];
sync_bit = sigmaps[sync_bit.wire->module](sync_bit);
}
pool<std::string> events;
switch (sync->type) {
case RTLIL::STp:
log_assert(sync_bit.wire != nullptr);
events.insert("posedge_" + mangle(sync_bit));
break;
case RTLIL::STn:
log_assert(sync_bit.wire != nullptr);
events.insert("negedge_" + mangle(sync_bit));
break;
case RTLIL::STe:
log_assert(sync_bit.wire != nullptr);
events.insert("posedge_" + mangle(sync_bit));
events.insert("negedge_" + mangle(sync_bit));
break;
case RTLIL::STa:
events.insert("true");
break;
case RTLIL::ST0:
case RTLIL::ST1:
case RTLIL::STa:
case RTLIL::STg:
case RTLIL::STi:
log_assert(false);