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5485 Commits

Author SHA1 Message Date
Eddie Hung c9a0bac541 IS_C_INVERTED 2019-06-03 19:45:56 -07:00
Eddie Hung ebcc85b9b8 Fix `ifndef 2019-06-03 12:37:02 -07:00
Eddie Hung 0092770317 Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now) 2019-06-03 12:34:55 -07:00
Eddie Hung d018cd9fe3 Assert that box_unique_id is indeed unique 2019-06-03 12:33:47 -07:00
Eddie Hung 295bd8d0bf Remove dupe 2019-06-03 12:32:20 -07:00
Eddie Hung a54822b1bc Skip internal modules when generating box_unique_id 2019-06-03 12:31:23 -07:00
Eddie Hung 257f7ff5f6 When creating new holes cell, inherit parameters too 2019-06-03 12:30:54 -07:00
Eddie Hung 4da25c76b3 Ooopsie 2019-06-03 09:33:42 -07:00
Eddie Hung 9f44a71715 Consistent with xilinx 2019-06-03 09:23:43 -07:00
Eddie Hung 2228cef62f Add flops as blackboxes 2019-05-31 18:11:46 -07:00
Eddie Hung 01f71085f2 Add FD*E_1 -> FD*E techmap rules 2019-05-31 18:11:24 -07:00
Eddie Hung dea36d4366 Techmap flops before ABC again 2019-05-31 18:10:25 -07:00
Eddie Hung e3d160a9ca parse_xaiger to cope with flops 2019-05-31 18:06:36 -07:00
Eddie Hung 4623177655 ABC9 to understand flops 2019-05-31 15:23:33 -07:00
Eddie Hung eb08e71bd1 Merge branch 'xaig' into xc7mux 2019-05-31 13:03:03 -07:00
Eddie Hung a379234f56 Throw out unused code inherited from abc 2019-05-31 12:50:11 -07:00
Eddie Hung 887c31f33b Fix issue where keep signal became PI, but also box was adding CI driver 2019-05-30 16:03:22 -07:00
Eddie Hung a41553a861 read_xaiger() to name box signals 2019-05-30 16:02:40 -07:00
Eddie Hung 4a6b9af227 Fix spelling 2019-05-30 15:50:47 -07:00
Eddie Hung 1ad33c3b5a Remove whitebox attribute from DRAMs for now 2019-05-30 13:07:29 -07:00
Eddie Hung e3c8132d7a Do not re-sort box_module ports 2019-05-30 12:26:51 -07:00
Eddie Hung c6fa4faa37 Remove whitespace 2019-05-30 12:25:21 -07:00
Eddie Hung a44fe3a632 Revert "Re-enable &dc2" 
This reverts commit 8c58c728a7.
 2019-05-30 11:41:50 -07:00
Eddie Hung 0800846e73 Do not double count LUT1s 2019-05-30 11:32:14 -07:00
Eddie Hung fdfc18be91 Carry in/out to be the last input/output for chains to be preserved 2019-05-30 01:23:36 -07:00
Eddie Hung 8c58c728a7 Re-enable &dc2 2019-05-30 00:42:41 -07:00
Eddie Hung 2560f92f29 Reduce -W to 160 2019-05-29 23:01:46 -07:00
Eddie Hung 276f5f8b81 Some more realistic delays... 2019-05-29 22:55:34 -07:00
Eddie Hung 854557814e Erase all boxes before stitching 2019-05-29 19:17:36 -07:00
Eddie Hung b955344ecd Call &if with -W 250 2019-05-29 16:34:52 -07:00
Eddie Hung 5e75abf870 Bump ABC 2019-05-29 16:34:43 -07:00
Eddie Hung 25befbf542 Rename to #23 2019-05-29 15:26:33 -07:00
Eddie Hung aa2380c17a Add abc_test024 2019-05-29 15:24:38 -07:00
Eddie Hung 1423384367 Fix abc_test024 2019-05-29 15:24:09 -07:00
Eddie Hung ecaa7856e9 Add some debug to abc9 2019-05-29 15:21:41 -07:00
Eddie Hung 92197326b8 Add abc9_test022 2019-05-28 12:43:07 -07:00
Eddie Hung b4321a31bb Fix for abc9_test022 2019-05-28 12:42:17 -07:00
Eddie Hung 13e233217c Small improvement 2019-05-28 11:29:59 -07:00
Eddie Hung 5f39c262c2 From master 2019-05-28 09:38:58 -07:00
Eddie Hung cdedf51c32 From master 2019-05-28 09:37:50 -07:00
Eddie Hung f228621b80 Typo 2019-05-28 09:36:01 -07:00
Eddie Hung 914074a07c Update from master 2019-05-28 09:35:45 -07:00
Eddie Hung 6931a3a47d Update README.md from master 2019-05-28 09:32:18 -07:00
Eddie Hung ba9513b325 Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-28 09:30:53 -07:00
Eddie Hung f745727de5 read_aiger to only clean own design 2019-05-28 08:45:10 -07:00
Eddie Hung 4a76b425cc Misspell 2019-05-28 08:44:59 -07:00
Clifford Wolf 8e647901ef
Merge pull request #1050 from YosysHQ/clifford/wandwor 
Refactored wand/wor support
 2019-05-28 17:42:16 +02:00
Clifford Wolf 49d641d97f
Merge pull request #1048 from mmicko/fix_enable_pyosys 
Moved pyosys block in Makefile
 2019-05-28 16:52:40 +02:00
Clifford Wolf ba2185ead8 Refactor hierarchy wand/wor handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 16:43:25 +02:00
Clifford Wolf e3ebac44df Add actual wandwor test that is part of "make test" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 16:42:50 +02:00