mirror of https://github.com/YosysHQ/yosys.git
read_aiger to only clean own design
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@ -722,8 +722,14 @@ void AigerReader::post_process()
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module->fixup_ports();
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design->add(module);
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design->selection_stack.emplace_back(false);
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RTLIL::Selection& sel = design->selection_stack.back();
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sel.select(module);
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Pass::call(design, "clean");
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design->selection_stack.pop_back();
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for (auto cell : module->cells().to_vector()) {
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if (cell->type != "$lut") continue;
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auto y_port = cell->getPort("\\Y").as_bit();
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