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58 Commits

Author SHA1 Message Date
Marcelina Kościelnicka 38a0c30d65 Get rid of dffsr2dff. 
This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part.  Thus, it never
actually does anything and can be safely removed.
 2020-04-15 16:22:37 +02:00
Miodrag Milanovic 0d789c5a3b Support custom PROGRAM_PREFIX 2020-04-10 10:38:40 +02:00
Gabriel Somlo 8106c3d31b abc9: restore ability to use ABCEXTERNAL 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-01-30 15:12:43 -05:00
Eddie Hung cf3a13746d Add abc9_ops -reintegrate; moved out from now abc9_exe 2020-01-06 15:52:59 -08:00
Eddie Hung f348ffa44d abc9_techmap -> _map; called from abc9 script pass along with abc9_ops 2019-12-28 05:07:46 -08:00
Eddie Hung ec25394808 Rename abc9.cc -> abc9_techmap.cc 2019-12-28 03:16:28 -08:00
Marcin Kościelnicki c9f9518de4 Added extractinv pass 2019-09-19 04:02:48 +02:00
Marcin Kościelnicki f4c62f33ac Add clock buffer insertion pass, improve iopadmap. 
A few new attributes are defined for use in cell libraries:

- iopad_external_pin: marks PAD cell's external-facing pin.  Pad
  insertion will be skipped for ports that are already connected
  to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
  buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
  Clock buffer insertion will be skipped for nets that are already
  driven by such a pin.

All three are module attributes that should be set to a comma-separeted
list of pin names.

Clock buffer insertion itself works as follows:

1. All cell ports, starting from bottom up, can be marked as clock sinks
   (requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
   buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
   contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
   also connected to a clock sink port in a contained cell, a clock
   buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
   connected to clock sinks, optionally with a special kind of input
   PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
   attribute is set on it.
 2019-08-13 00:16:38 +02:00
Gabriel L. Somlo 8cb3655ecd Make abc9 pass aware of optional ABCEXTERNAL override 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-06-28 14:56:16 -04:00
Eddie Hung 5a0a5aae4f Compile abc9 2019-02-08 13:58:47 -08:00
whitequark 07af772a72 flowmap: new techmap pass. 2019-01-03 14:28:19 +00:00
David Shah 459d367913 ecp5: Adding synchronous set/reset support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-14 16:18:01 +02:00
Andrew Zonenberg b5c15636c5 Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass 2017-08-28 22:18:34 -07:00
Clifford Wolf 908f34aafc Rename recover_reduce to extract_reduce, fix args handling 2017-08-28 19:52:06 +02:00
Robert Ou 8a5887464c recover_reduce: Rename recover_reduce_core to recover_reduce 
Clifford has commented on PR #387 stating that he does not like the
driver script and would prefer to only have the core script with
appropriate notes in the documentation.

Also rename to .cc (rather than .cpp) for consistency.
 2017-08-27 02:01:32 -07:00
Robert Ou 99dad40ed0 recover_reduce: Add driver script for the $reduce_* recover feature 
Conflicts:
	passes/techmap/Makefile.inc
 2017-08-27 01:57:20 -07:00
Robert Ou fa310c98f8 recover_reduce_core: Initial commit 
Conflicts:
	passes/techmap/Makefile.inc
 2017-08-27 01:56:49 -07:00
Clifford Wolf 0bf612506c Rename "adders" to "extract_fa" 2017-08-25 12:04:40 +02:00
Clifford Wolf 51cbec7f75 Add experimental adders pass 2017-08-22 13:52:13 +02:00
Clifford Wolf ee91350add Added "zinit" pass 2016-10-12 12:05:19 +02:00
Clifford Wolf b0aab4e304 Added "attrmap" command 2016-08-09 19:56:55 +02:00
Clifford Wolf 3c6d31fd06 Added "attrmvcp" pass 2016-08-09 11:18:48 +02:00
Clifford Wolf 5d6765a9d2 Added "insbuf" command 2016-08-02 10:37:19 +02:00
Clifford Wolf ca91bccb6b Added "deminout" 2016-06-19 13:08:16 +02:00
Clifford Wolf de647a390c Added "shregmap" pass 2016-04-16 23:20:49 +02:00
Clifford Wolf bb9374b67c Improvements in ABCEXTERNAL handling 2016-03-19 20:02:40 +01:00
Clifford Wolf d69395ca08 Added dffsr2dff 2016-02-02 17:19:01 +01:00
Clifford Wolf 71f418c468 More clang sanitizer stuff 2016-01-31 19:55:48 +01:00
Clifford Wolf 598a475724 Added nlutmap 2015-09-18 21:57:34 +02:00
Clifford Wolf c851f51656 Added lut2mux pass 2015-09-18 21:55:48 +02:00
Clifford Wolf 9c33172ece Added tribuf command 2015-08-16 12:55:25 +02:00
Clifford Wolf e4ef000b70 Adjust makefiles to work with out-of-tree builds 
This is based on work done by Larry Doolittle
 2015-08-12 15:04:44 +02:00
Clifford Wolf 56d4822719 Renamed "aig" to "aigmap" 2015-06-10 07:24:26 +02:00
Clifford Wolf 66f9ee412a Added "aig" pass 2015-06-09 22:33:26 +02:00
Clifford Wolf 7dad017c9c abc/blifparse files reorganization 2015-05-17 14:44:28 +02:00
Clifford Wolf 724cead61d Added "pmuxtree" command 2015-04-07 20:27:10 +02:00
Clifford Wolf f7fb21f185 Added "muxcover" command 2015-04-07 15:42:25 +02:00
Clifford Wolf c52a4cdeed Added "dffinit", Support for initialized Xilinx DFF 2015-04-04 19:00:15 +02:00
Clifford Wolf 3216f9420e More emscripten stuff, Added example app 2015-02-15 12:09:30 +01:00
Clifford Wolf c64b1de11d Fixed build with SMALL=1 2014-12-30 11:41:24 +01:00
Clifford Wolf 97487fee32 Added skeleton dff2dffe pass 2014-12-08 14:10:52 +01:00
Clifford Wolf 973d376733 Added genfiles.zip to MXE "make dist" 2014-10-17 12:11:15 +02:00
Clifford Wolf ccf7b2e342 Added mxe-based cross build for win32 2014-10-09 10:50:44 +02:00
Clifford Wolf ff157fb74f alumacc skeleton 2014-09-14 10:02:00 +02:00
Clifford Wolf 015dcdc84c Added "maccmap" command 2014-09-07 18:23:04 +02:00
Clifford Wolf 1202f7aa4b Renamed "stdcells.v" to "techmap.v" 2014-07-31 02:32:00 +02:00
Clifford Wolf 45b4154b37 Added "make SMALL=1" 2014-07-24 19:03:57 +02:00
Clifford Wolf b17d6531c8 Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
Clifford Wolf 9087ece97c OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:52:37 +01:00
Clifford Wolf 6644f80d97 Moved some passes to other source directories 2014-02-08 14:39:15 +01:00