Clifford Wolf
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b9f2127f5d
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Various documentation updates
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2014-11-08 10:59:48 +01:00 |
Clifford Wolf
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420bc05627
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Added "Nx" syntax to "show" command for repeating SigChunks
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2014-11-08 10:58:57 +01:00 |
Clifford Wolf
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89be7bf527
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Added "used" attribute to entries in yosys_cover_list
http://www.reddit.com/r/yosys/comments/2kw479/fyi_clang_350_build_error/cltgwyc
http://llvm.org/bugs/show_bug.cgi?id=19474
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2014-11-07 20:58:08 +01:00 |
Clifford Wolf
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c5dbb1aa28
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Minor corrections in CodingReadme
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2014-11-07 15:47:18 +01:00 |
Clifford Wolf
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546e8b5fe7
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Improved TopoSort determinism
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2014-11-07 15:21:03 +01:00 |
Clifford Wolf
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461594bb83
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Fixed generation of temp names in verilog backend
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2014-11-07 14:40:06 +01:00 |
Clifford Wolf
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4f4d729e02
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Updated ABC to 5b5af75f1dda
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2014-11-07 14:39:49 +01:00 |
Clifford Wolf
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c529d4fc53
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Changelog for Yosys 0.4
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2014-11-07 13:34:05 +01:00 |
Clifford Wolf
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99cdfb3110
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Fixed typo in "log_cmd_error_exception"
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2014-11-07 12:48:15 +01:00 |
Clifford Wolf
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a346c0bf2b
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Made "cover" a compile-time option (disabled by default)
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2014-11-06 09:39:55 +01:00 |
Clifford Wolf
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80869531b9
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Removed QMAKE variable from Makefile
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2014-11-05 10:37:37 +01:00 |
Clifford Wolf
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74ef92b9c8
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Added "abc" label in synth script
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2014-10-31 03:46:27 +01:00 |
Clifford Wolf
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ab28491f27
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Added "opt -full" alias for all more aggressive optimizations
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2014-10-31 03:36:51 +01:00 |
Clifford Wolf
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a21481b338
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Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."
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2014-10-30 14:01:02 +01:00 |
Clifford Wolf
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ac8f4d298b
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Improved nomem2reg documentation
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2014-10-30 09:12:55 +01:00 |
Clifford Wolf
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269e37e969
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Added support for empty lines to here documents
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2014-10-29 09:05:17 +01:00 |
Clifford Wolf
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37aa2e02db
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AST simplifier: optimize constant AST_CASE nodes before recursively descending
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2014-10-29 08:29:51 +01:00 |
Clifford Wolf
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f9c096eeda
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Added support for task and function args in parentheses
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2014-10-27 13:21:57 +01:00 |
Clifford Wolf
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c4a2b3c1e9
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Improvements in $readmem[bh] implementation
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2014-10-26 23:29:36 +01:00 |
Clifford Wolf
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70b2efdb05
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Added support for $readmemh/$readmemb
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2014-10-26 20:33:10 +01:00 |
Clifford Wolf
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26cbe4a4e5
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Fixed constant "cond ? string1 : string2" with strings of different size
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2014-10-25 18:23:53 +02:00 |
Clifford Wolf
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c5eb5e56b8
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Re-introduced Yosys::readsome() helper function
(f.read() + f.gcount() made problems with lines > 16kB)
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2014-10-23 10:58:36 +02:00 |
Clifford Wolf
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750c615e7f
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minor indenting corrections
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2014-10-19 18:42:03 +02:00 |
Clifford Wolf
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3202ba621c
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Merge pull request #40 from parvizp/compile_mac_10.9.2
Builds on Mac 10.9.2 with LLVM 3.5.
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2014-10-19 18:40:22 +02:00 |
Parviz Palangpour
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de8adb8ec5
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Builds on Mac 10.9.2 with LLVM 3.5.
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2014-10-19 11:14:43 -05:00 |
Clifford Wolf
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6c1c1e9a07
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Improved new_id() for win32
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2014-10-18 19:26:03 +02:00 |
Clifford Wolf
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bb631c6f5c
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Also look for yosys-abc in parent dir on win32
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2014-10-18 19:01:44 +02:00 |
Clifford Wolf
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0471d158d9
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Various improvements to version reporting on win32
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2014-10-18 19:00:52 +02:00 |
Clifford Wolf
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57cd485236
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Disabled READLINE in MXE cross build
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2014-10-18 18:21:33 +02:00 |
Clifford Wolf
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41db98ba31
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Fixed typo in test_cell
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2014-10-18 16:52:06 +01:00 |
Clifford Wolf
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6bcb4f1f45
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Fixed shell prompt and proc_self_dirname() for win32
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2014-10-18 16:51:50 +01:00 |
Clifford Wolf
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84ffe04075
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Fixed various VS warnings
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2014-10-18 15:20:38 +02:00 |
Clifford Wolf
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85572b05e5
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Create vcxsrc in mxe build "make dist"
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2014-10-18 15:17:33 +02:00 |
Clifford Wolf
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b5da3a60e1
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Moved yosys-config.in to misc/
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2014-10-18 14:15:05 +02:00 |
Clifford Wolf
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c321b419d4
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Added notes regarding building in VS
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2014-10-17 16:39:24 +02:00 |
Clifford Wolf
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e8a609f0e5
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Added vcxproj_files.txt to MXE "make dist"
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2014-10-17 16:05:00 +02:00 |
Clifford Wolf
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b3a6f8f530
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More win32 (mxe and vs) build fixes
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2014-10-17 16:04:59 +02:00 |
Clifford Wolf
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468ae92374
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Various win32 / vs build fixes
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2014-10-17 14:01:47 +02:00 |
Clifford Wolf
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973d376733
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Added genfiles.zip to MXE "make dist"
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2014-10-17 12:11:15 +02:00 |
Clifford Wolf
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4df902637a
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Various MXE build fixes
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2014-10-17 12:04:40 +02:00 |
William Speirs
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31267a1ae8
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Header changes so it will compile on VS
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2014-10-17 11:41:36 +02:00 |
William Speirs
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fda52f05f2
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Wrapped math in int constructor
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2014-10-17 11:28:14 +02:00 |
Clifford Wolf
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34caeeb4f3
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Fixed a few VS warnings
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2014-10-17 06:02:38 +02:00 |
Clifford Wolf
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18cb8b4636
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Don't be too smart with $dff cells with "init" attribute on out signal
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2014-10-16 11:49:31 +02:00 |
Clifford Wolf
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66eb254fc2
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Some cleanups in opt_clean
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2014-10-16 11:46:57 +02:00 |
Clifford Wolf
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3838856a9e
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Print "SystemVerilog" in "read_verilog -sv" log messages
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2014-10-16 10:31:54 +02:00 |
Clifford Wolf
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3be5fa053f
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Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selects
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2014-10-16 00:54:14 +02:00 |
Clifford Wolf
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6b05a9e807
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Fixed handling of invalid array access in mem2reg code
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2014-10-16 00:44:23 +02:00 |
Clifford Wolf
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82ed814fa1
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Replaced log_assert() do { ... } while (0) hack with a static inline function
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2014-10-15 20:36:32 +02:00 |
Clifford Wolf
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2355ddf75d
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Fixed gcc warning
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2014-10-15 02:48:51 +02:00 |