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Changelog for Yosys 0.4
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CHANGELOG
81
CHANGELOG
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@ -3,13 +3,82 @@ List of changes and major improvements between releases
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=======================================================
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Yosys 0.3.0 .. Yoys 0.3.0+
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--------------------------
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Yosys 0.3.0 .. Yosys 0.4
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------------------------
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... TBD ...
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* Platform Support
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- Added support for mxe-based cross-builds for win32
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- Added sourcecode-export as VisualStudio project
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- Added experimental EMCC (JavaScript) support
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* Verilog Frontend
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- Added -sv option for SystemVerilog (and automatic *.sv file support)
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- Added support for real-valued constants and constant expressions
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- Added support for non-standard "via_celltype" attribute on task/func
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- Added support for non-standard "module mod_name(...);" syntax
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- Added support for non-standard """ macro bodies
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- Added support for array with more than one dimension
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- Added support for $readmemh and $readmemb
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- Added support for DPI functions
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* Changes in internal cell library
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- Added $shift and $shiftx cell types
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- Added $alu, $lcu, $fa and $macc cell types
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- Removed $bu0 and $safe_pmux cell types
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- $mem/$memwr WR_EN input is now a per-data-bit enable signal
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- Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
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- Renamed ports of $lut cells (from I->O to A->Y)
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- Renamed $_INV_ to $_NOT_
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* Changes for simple synthesis flows
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- There is now a "synth" command with a recommended default script
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- Many improvements in synthesis of arithmetic functions to gates
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- Multiplieres and adders with many operands are using carry-save adder trees
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- Remaining adders are now implemented using Brent–Kung carry look-ahead adders
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- Various new high-level optimizations on RTL netlist
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- Various improvements in FSM optimization
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- Updated ABC to hg 930a4de962a1 (from 2014-10-14)
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* Changes in internal APIs and RTLIL
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- Added log_id() and log_cell() helper functions
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- Added function-like cell creation helpers
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- Added GetSize() function (like .size() but with int)
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- Major refactoring of RTLIL::Module and related classes
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- Major refactoring of RTLIL::SigSpec and related classes
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- Now RTLIL::IdString is essentially an int
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- Added macros for code coverage counters
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- Added some Makefile magic for pretty make logs
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- Added "kernel/yosys.h" with all the core definitions
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- Chanded a lot of code from FILE* to c++ streams
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- Added RTLIL::Monitor API and "trace" command
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- Added "Yosys" C++ namespace
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* Changes relevant to SAT solving
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- Added ezSAT::keep_cnf() and ezSAT::non_incremental()
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- Added native ezSAT support for vector shift ops
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- Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
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* New commands (or large improvements to commands)
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- Added "synth" command with default script
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- Added "share" (finally some real resource sharing)
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- Added "memory_share" (reduce number of ports on memories)
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- Added "wreduce" and "alumacc" commands
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- Added "opt -keepdc -fine -full -fast"
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- Added some "test_*" commands
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* Various other changes
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- Added %D and %c select operators
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- Added support for labels in yosys scripts
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- Added support for here-documents in yosys scripts
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- Support "+/" prefix for files from proc_share_dir
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- Added "autoidx" statement to ilang language
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- Switched from "yosys-svgviewer" to "xdot"
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- Renamed "stdcells.v" to "techmap.v"
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- Various bug fixes and small improvements
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- Improved welcome and bye messages
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Yosys 0.2.0 .. Yoys 0.3.0
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Yosys 0.2.0 .. Yosys 0.3.0
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--------------------------
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* Driver program and overall behavior:
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@ -59,8 +128,8 @@ Yosys 0.2.0 .. Yoys 0.3.0
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- Various build fixes for OSX (Darwin) and OpenBSD
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Yosys 0.1.0 .. Yoys 0.2.0
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-------------------------
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Yosys 0.1.0 .. Yosys 0.2.0
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--------------------------
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* Changes to the driver program:
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- Added "yosys -h" and "yosys -H"
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