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2,063 Commits 114 Branches 50 Tags 34 MiB
Commit Graph

159 Commits

Author SHA1 Message Date
Clifford Wolf 853e949c0e Disabled (unused) Xilinx tristate buffers 2015-02-04 16:33:59 +01:00
Clifford Wolf bebbf2e5a4 no support for 6-series xilinx devices 2015-02-01 23:06:44 +01:00
Clifford Wolf 3cbfa3815e Removed old XST-based xilinx examples 2015-02-01 17:10:46 +01:00
Clifford Wolf 816fe6bbe0 Added Xilinx example for Basys3 board 2015-02-01 17:09:34 +01:00
Clifford Wolf 1b159bc955 Added missing ports and parameters to xilinx brams 2015-02-01 15:42:59 +01:00
Clifford Wolf 1df81f92ce Added "make mklibyosys", some minor API changes 2015-02-01 13:38:46 +01:00
Clifford Wolf bedd46338f Added "fsm -encfile" 2015-01-30 22:46:53 +01:00
Clifford Wolf 909a95182b Fixed xilinx FDSE sim model 2015-01-24 11:03:22 +01:00
Clifford Wolf e13a45ae61 Added $equiv cell type 2015-01-19 11:55:05 +01:00
Clifford Wolf d29d26f882 Various cleanups in xilinx techlib 2015-01-18 19:43:54 +01:00
Clifford Wolf 8d295730e5 Refactoring of memory_bram and xilinx brams 2015-01-18 19:05:29 +01:00
Clifford Wolf 279a18c9a3 Added synth_xilinx -retime -flatten 2015-01-17 20:47:18 +01:00
Clifford Wolf 7031231145 Added MUXCY and XORCY support to synth_xilinx 2015-01-17 15:39:54 +01:00
Clifford Wolf 3ed4e34380 Added cells.lib 2015-01-16 15:50:42 +01:00
Clifford Wolf dff8bd3b2a Added dff2dffe to synth_xilinx 2015-01-16 15:49:15 +01:00
Clifford Wolf 7bde74cd2a Added more FF types to xilinx/cells.v 2015-01-16 15:24:54 +01:00
Clifford Wolf 6b09153320 Fixed xilinx bram clock inverted config 2015-01-16 15:11:56 +01:00
Clifford Wolf fd8c8d4fd3 Added FF cells to xilinx/cells_sim.v 2015-01-16 14:59:40 +01:00
Clifford Wolf b197279f3c Added Xilinx MUXF7 and MUXF8 support 2015-01-15 13:50:04 +01:00
Clifford Wolf 153d3dd4e0 Various cleanups in synth_xilinx command 2015-01-13 13:20:32 +01:00
Clifford Wolf 1d96277f5d Added add_share_file Makefile macro 2015-01-08 00:23:18 +01:00
Clifford Wolf 38dfc5c580 added minimalistic xilinx sim models 2015-01-08 00:05:11 +01:00
Clifford Wolf d1e38693d5 More Xilinx bram cleanups 2015-01-07 01:59:36 +01:00
Clifford Wolf 584c5f3937 Cleanups in xilinx bram descriptions 2015-01-07 01:28:18 +01:00
Clifford Wolf 08c13f635c Xilinx RAMB36/RAMB18 memory_bram support complete 2015-01-06 23:54:33 +01:00
Clifford Wolf ec2eef89fa Towards Xilinx bram support 2015-01-06 23:21:52 +01:00
Clifford Wolf 7cc5192125 small fix in xilinx/brams.v 2015-01-06 17:21:18 +01:00
Clifford Wolf 9474928672 Towards Xilinx bram support 2015-01-06 15:26:33 +01:00
Clifford Wolf 4a0b3a5423 Various small improvements to synth_xilinx 2015-01-06 14:37:50 +01:00
Clifford Wolf 081e1a49f8 Towards Xilinx bram support 2015-01-06 14:26:51 +01:00
Clifford Wolf 9c7f47bbd5 Towards Xilinx bram support 2015-01-06 13:33:51 +01:00
Clifford Wolf 9ea2511fe8 Towards Xilinx bram support 2015-01-05 13:59:04 +01:00
Clifford Wolf 8898897f7b Towards Xilinx bram support 2015-01-04 14:23:30 +01:00
Clifford Wolf a7e43ae3d9 Progress in memory_bram 2015-01-03 10:57:01 +01:00
Clifford Wolf 90f4017703 Added proper clkpol support to memory_bram 2015-01-02 22:57:08 +01:00
Clifford Wolf 474831643c New $mem simlib model 2015-01-02 17:11:31 +01:00
Clifford Wolf 327a5d42b6 Progress in memory_bram 2014-12-31 22:50:08 +01:00
Clifford Wolf 94e6b70736 Added memory_bram (not functional yet) 2014-12-31 16:53:53 +01:00
Clifford Wolf ba43cf5807 Fixed simlib entries for $memrd and $memwr 2014-12-30 13:33:29 +01:00
Clifford Wolf c64b1de11d Fixed build with SMALL=1 2014-12-30 11:41:24 +01:00
Clifford Wolf 4aa9fbbf3f Improvements in simplemap api, added $ne $nex $eq $eqx support 2014-12-24 10:49:24 +01:00
Clifford Wolf 72f500c950 Removed UTF-8 chars from techmap.v 2014-12-12 12:44:16 +01:00
Clifford Wolf f1764b4fe9 Added $dffe cell type 2014-12-08 10:50:19 +01:00
Clifford Wolf fad9cec47b Added $_DFFE_??_ cell types 2014-12-08 10:43:38 +01:00
Clifford Wolf 74ef92b9c8 Added "abc" label in synth script 2014-10-31 03:46:27 +01:00
Clifford Wolf ab28491f27 Added "opt -full" alias for all more aggressive optimizations 2014-10-31 03:36:51 +01:00
Clifford Wolf c3e779a65f Added $_BUF_ cell type 2014-10-03 10:12:28 +02:00
Clifford Wolf f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf 4888d61c65 Improvements in "synth" script 2014-09-18 12:57:55 +02:00
Clifford Wolf 6644e27cd4 Fixed $macc simlib model for zero-config 2014-09-16 08:19:35 +02:00